Search

Hiep T. Nguyen

Examiner (ID: 18287, Phone: (571)272-4197 , Office: P/2131 )

Most Active Art Unit
2187
Art Unit(s)
2187, 2131, 2759, 2751, 2137, 2188, 2312, 2138
Total Applications
2185
Issued Applications
1977
Pending Applications
88
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10616497 [patent_doc_number] => 09335941 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Crash consistency' [patent_app_type] => utility [patent_app_number] => 14/630939 [patent_app_country] => US [patent_app_date] => 2015-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 6684 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14630939 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/630939
Crash consistency Feb 24, 2015 Issued
Array ( [id] => 12153504 [patent_doc_number] => 20180024768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'PARTITIONING MEMORY MODULES INTO VOLATILE AND NON-VOLATILE PORTIONS' [patent_app_type] => utility [patent_app_number] => 15/549724 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3777 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15549724 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/549724
PARTITIONING MEMORY MODULES INTO VOLATILE AND NON-VOLATILE PORTIONS Feb 12, 2015 Abandoned
Array ( [id] => 11810773 [patent_doc_number] => 09715344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Memory device and controlling method of the same' [patent_app_type] => utility [patent_app_number] => 14/620305 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12861 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620305 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620305
Memory device and controlling method of the same Feb 11, 2015 Issued
Array ( [id] => 10724323 [patent_doc_number] => 20160070471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/620814 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5433 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620814 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620814
Memory system Feb 11, 2015 Issued
Array ( [id] => 11042463 [patent_doc_number] => 20160239419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'MEMORY NEST EFFICIENCY WITH CACHE DEMAND GENERATION' [patent_app_type] => utility [patent_app_number] => 14/620240 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620240 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620240
Memory nest efficiency with cache demand generation Feb 11, 2015 Issued
Array ( [id] => 10392780 [patent_doc_number] => 20150277787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/620332 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4244 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620332 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620332
Memory controller, memory system, and memory control method Feb 11, 2015 Issued
Array ( [id] => 10637309 [patent_doc_number] => 09354812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-31 [patent_title] => 'Dynamic memory utilization in a system on a chip' [patent_app_type] => utility [patent_app_number] => 14/620797 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7271 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620797 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620797
Dynamic memory utilization in a system on a chip Feb 11, 2015 Issued
Array ( [id] => 11816652 [patent_doc_number] => 09720601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Load balancing technique for a storage array' [patent_app_type] => utility [patent_app_number] => 14/619934 [patent_app_country] => US [patent_app_date] => 2015-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14619934 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/619934
Load balancing technique for a storage array Feb 10, 2015 Issued
Array ( [id] => 13269305 [patent_doc_number] => 10146737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Gather using index array and finite state machine [patent_app_type] => utility [patent_app_number] => 14/616323 [patent_app_country] => US [patent_app_date] => 2015-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 19261 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14616323 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/616323
Gather using index array and finite state machine Feb 5, 2015 Issued
Array ( [id] => 12985861 [patent_doc_number] => 20170344313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => STORAGE SYSTEM AND CONTROL METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/537895 [patent_app_country] => US [patent_app_date] => 2015-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15537895 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/537895
Storage system and control method therefor Jan 22, 2015 Issued
Array ( [id] => 11897929 [patent_doc_number] => 09767868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses' [patent_app_type] => utility [patent_app_number] => 14/589145 [patent_app_country] => US [patent_app_date] => 2015-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4983 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14589145 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/589145
Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses Jan 4, 2015 Issued
Array ( [id] => 10157389 [patent_doc_number] => 09189164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Secure memory system with fast wipe feature' [patent_app_type] => utility [patent_app_number] => 14/588401 [patent_app_country] => US [patent_app_date] => 2014-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 83 [patent_no_of_words] => 43802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14588401 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/588401
Secure memory system with fast wipe feature Dec 30, 2014 Issued
Array ( [id] => 10991285 [patent_doc_number] => 20160188230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'DIAGONAL ANTI-DIAGONAL MEMORY STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/583738 [patent_app_country] => US [patent_app_date] => 2014-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 15320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583738 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583738
Diagonal anti-diagonal memory structure Dec 27, 2014 Issued
Array ( [id] => 10616694 [patent_doc_number] => 09336140 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Efficient management of hierarchically-linked data storage spaces' [patent_app_type] => utility [patent_app_number] => 14/583711 [patent_app_country] => US [patent_app_date] => 2014-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583711
Efficient management of hierarchically-linked data storage spaces Dec 27, 2014 Issued
Array ( [id] => 10991285 [patent_doc_number] => 20160188230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'DIAGONAL ANTI-DIAGONAL MEMORY STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/583738 [patent_app_country] => US [patent_app_date] => 2014-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 15320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583738 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583738
Diagonal anti-diagonal memory structure Dec 27, 2014 Issued
Array ( [id] => 10991546 [patent_doc_number] => 20160188492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'Memory Protection with Non-Readable Pages' [patent_app_type] => utility [patent_app_number] => 14/583681 [patent_app_country] => US [patent_app_date] => 2014-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10529 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583681 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583681
Memory protection with non-readable pages Dec 26, 2014 Issued
Array ( [id] => 10991547 [patent_doc_number] => 20160188491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'APPARATUS AND METHOD FOR ASYNCHRONOUS TILE-BASED RENDERING CONTROL' [patent_app_type] => utility [patent_app_number] => 14/582790 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10738 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/582790
Apparatus and method for asynchronous tile-based rendering control Dec 23, 2014 Issued
Array ( [id] => 11200180 [patent_doc_number] => 09430393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'System and method for managing cache' [patent_app_type] => utility [patent_app_number] => 14/583020 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583020
System and method for managing cache Dec 23, 2014 Issued
Array ( [id] => 10991469 [patent_doc_number] => 20160188414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'FAULT TOLERANT AUTOMATIC DUAL IN-LINE MEMORY MODULE REFRESH' [patent_app_type] => utility [patent_app_number] => 14/583037 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8558 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583037 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583037
FAULT TOLERANT AUTOMATIC DUAL IN-LINE MEMORY MODULE REFRESH Dec 23, 2014 Abandoned
Array ( [id] => 11226606 [patent_doc_number] => 09454328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Controlling hierarchical storage' [patent_app_type] => utility [patent_app_number] => 14/582804 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582804 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/582804
Controlling hierarchical storage Dec 23, 2014 Issued
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