Hieu C. Le

Array ( [id] => 3867203 [patent_doc_number] => 05768214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/689548 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5741 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768214.pdf [firstpage_image] =>[orig_patent_app_number] => 689548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4012203 [patent_doc_number] => 05986946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method and apparatus for reducing row shut-off time in an interleaved-row memory device' [patent_app_type] => 1 [patent_app_number] => 8/692950 [patent_app_country] => US [patent_app_date] => 1996-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3273 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986946.pdf [firstpage_image] =>[orig_patent_app_number] => 692950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3789507 [patent_doc_number] => 05808959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Staggered pipeline access scheme for synchronous random access memory' [patent_app_type] => 1 [patent_app_number] => 8/612044 [patent_app_country] => US [patent_app_date] => 1996-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4587 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808959.pdf [firstpage_image] =>[orig_patent_app_number] => 612044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3844783 [patent_doc_number] => 05761145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Efficient method for obtaining usable parts from a partially good memory integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/685783 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4602 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761145.pdf [firstpage_image] =>[orig_patent_app_number] => 685783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3841321 [patent_doc_number] => 05712816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Method for evaluating the dielectric layer of nonvolatile EPROM, EEPROM and flash-EEPROM memories' [patent_app_type] => 1 [patent_app_number] => 8/685782 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4991 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712816.pdf [firstpage_image] =>[orig_patent_app_number] => 685782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836056 [patent_doc_number] => 05732021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Programmable and convertible non-volatile memory array' [patent_app_type] => 1 [patent_app_number] => 8/690244 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 6868 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732021.pdf [firstpage_image] =>[orig_patent_app_number] => 690244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3814466 [patent_doc_number] => 05831451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Dynamic logic circuits using transistors having differing threshold voltages' [patent_app_type] => 1 [patent_app_number] => 8/687800 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 34 [patent_no_of_words] => 30782 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831451.pdf [firstpage_image] =>[orig_patent_app_number] => 687800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3636958 [patent_doc_number] => RE035591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Memory cell array semiconductor integrated circuit device' [patent_app_type] => 2 [patent_app_number] => 8/679391 [patent_app_country] => US [patent_app_date] => 1996-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6952 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035591.pdf [firstpage_image] =>[orig_patent_app_number] => 679391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3712777 [patent_doc_number] => 05646902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Static random access memory device with low power dissipation' [patent_app_type] => 1 [patent_app_number] => 8/675511 [patent_app_country] => US [patent_app_date] => 1996-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3419 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646902.pdf [firstpage_image] =>[orig_patent_app_number] => 675511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3814508 [patent_doc_number] => 05831454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Emitter coupled logic (ECL) gate' [patent_app_type] => 1 [patent_app_number] => 8/673858 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3240 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831454.pdf [firstpage_image] =>[orig_patent_app_number] => 673858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3704158 [patent_doc_number] => 05680346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'High-speed, non-volatile electrically programmable and erasable cell and method' [patent_app_type] => 1 [patent_app_number] => 8/672299 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2316 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680346.pdf [firstpage_image] =>[orig_patent_app_number] => 672299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3888727 [patent_doc_number] => 05764574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method and apparatus for back-end repair of multi-chip modules' [patent_app_type] => 1 [patent_app_number] => 8/666247 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4152 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764574.pdf [firstpage_image] =>[orig_patent_app_number] => 666247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4233911 [patent_doc_number] => 06011717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'EEPROM memory programmable and erasable by Fowler-Nordheim effect' [patent_app_type] => 1 [patent_app_number] => 8/666849 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5888 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011717.pdf [firstpage_image] =>[orig_patent_app_number] => 666849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3844492 [patent_doc_number] => 05761123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Sense amplifier circuit of a nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/663350 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7358 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761123.pdf [firstpage_image] =>[orig_patent_app_number] => 663350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3852107 [patent_doc_number] => 05708618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Multiport field memory' [patent_app_type] => 1 [patent_app_number] => 8/658312 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5908 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708618.pdf [firstpage_image] =>[orig_patent_app_number] => 658312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3843763 [patent_doc_number] => 05740107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Nonvolatile integrated circuit memories having separate read/write paths' [patent_app_type] => 1 [patent_app_number] => 8/653344 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6736 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740107.pdf [firstpage_image] =>[orig_patent_app_number] => 653344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3780677 [patent_doc_number] => 05734602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Virtual ground read only memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/651233 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4135 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734602.pdf [firstpage_image] =>[orig_patent_app_number] => 651233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3747380 [patent_doc_number] => 05699303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Semiconductor memory device having controllable supplying capability of internal voltage' [patent_app_type] => 1 [patent_app_number] => 8/645347 [patent_app_country] => US [patent_app_date] => 1996-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 8781 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699303.pdf [firstpage_image] =>[orig_patent_app_number] => 645347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3937463 [patent_doc_number] => 05946261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Dual-port memory' [patent_app_type] => 1 [patent_app_number] => 8/643735 [patent_app_country] => US [patent_app_date] => 1996-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3465 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946261.pdf [firstpage_image] =>[orig_patent_app_number] => 643735 [rel_patent_id] =>[rel_patent_doc_number] =>)