Hieu C. Le

Array ( [id] => 3775300 [patent_doc_number] => RE035934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Semiconductor memory device synchronous with external clock signal for outputting data bits through a small number of data lines' [patent_app_type] => 2 [patent_app_number] => 8/879516 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8171 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 27 [patent_words_short_claim] => 505 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035934.pdf [firstpage_image] =>[orig_patent_app_number] => 879516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4073483 [patent_doc_number] => 05896341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Synchronous semiconductor memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/879215 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4705 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896341.pdf [firstpage_image] =>[orig_patent_app_number] => 879215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3994013 [patent_doc_number] => 05862094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Semiconductor device and a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/870547 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5218 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862094.pdf [firstpage_image] =>[orig_patent_app_number] => 870547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3821378 [patent_doc_number] => 05831915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Memory device with clocked column redundancy' [patent_app_type] => 1 [patent_app_number] => 8/868213 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4740 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831915.pdf [firstpage_image] =>[orig_patent_app_number] => 868213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3913139 [patent_doc_number] => 05751652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Semiconductor apparatus having a voltage unit and a backup unit for providing a reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 8/867044 [patent_app_country] => US [patent_app_date] => 1997-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13329 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751652.pdf [firstpage_image] =>[orig_patent_app_number] => 867044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3774738 [patent_doc_number] => 05844834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Single-electron memory cell configuration' [patent_app_type] => 1 [patent_app_number] => 8/867114 [patent_app_country] => US [patent_app_date] => 1997-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4320 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844834.pdf [firstpage_image] =>[orig_patent_app_number] => 867114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915154 [patent_doc_number] => 05898612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Magnetic memory cell with increased GMR ratio' [patent_app_type] => 1 [patent_app_number] => 8/861544 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3507 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898612.pdf [firstpage_image] =>[orig_patent_app_number] => 861544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3962285 [patent_doc_number] => 05956278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Semiconductor circuit device with internal power supply circuit' [patent_app_type] => 1 [patent_app_number] => 8/856445 [patent_app_country] => US [patent_app_date] => 1997-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 5473 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956278.pdf [firstpage_image] =>[orig_patent_app_number] => 856445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3772375 [patent_doc_number] => 05742545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Semiconductor memory device having function of preventing potential variation of read bus due to coupling' [patent_app_type] => 1 [patent_app_number] => 8/854450 [patent_app_country] => US [patent_app_date] => 1997-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4159 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742545.pdf [firstpage_image] =>[orig_patent_app_number] => 854450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3807869 [patent_doc_number] => 05781484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/852643 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 7867 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781484.pdf [firstpage_image] =>[orig_patent_app_number] => 852643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3883007 [patent_doc_number] => 05838624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Circuits for improving the reliability of antifuses in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/850902 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2934 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838624.pdf [firstpage_image] =>[orig_patent_app_number] => 850902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853909 [patent_doc_number] => 05848022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Address enable circuit in synchronous SRAM' [patent_app_type] => 1 [patent_app_number] => 8/850717 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5411 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848022.pdf [firstpage_image] =>[orig_patent_app_number] => 850717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3988567 [patent_doc_number] => 05917753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells' [patent_app_type] => 1 [patent_app_number] => 8/845916 [patent_app_country] => US [patent_app_date] => 1997-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2694 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917753.pdf [firstpage_image] =>[orig_patent_app_number] => 845916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3866624 [patent_doc_number] => 05768175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Ferroelectric memory with fault recovery circuits' [patent_app_type] => 1 [patent_app_number] => 8/839948 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2636 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768175.pdf [firstpage_image] =>[orig_patent_app_number] => 839948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3980604 [patent_doc_number] => 05886929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'High speed addressing buffer and methods for implementing same' [patent_app_type] => 1 [patent_app_number] => 8/837611 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7500 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886929.pdf [firstpage_image] =>[orig_patent_app_number] => 837611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3816061 [patent_doc_number] => 05854765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/845031 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6677 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854765.pdf [firstpage_image] =>[orig_patent_app_number] => 845031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892541 [patent_doc_number] => 05748546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Sensing scheme for flash memory with multilevel cells' [patent_app_type] => 1 [patent_app_number] => 8/827670 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5820 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748546.pdf [firstpage_image] =>[orig_patent_app_number] => 827670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3802440 [patent_doc_number] => 05841704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Static RAM' [patent_app_type] => 1 [patent_app_number] => 8/838782 [patent_app_country] => US [patent_app_date] => 1997-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4890 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841704.pdf [firstpage_image] =>[orig_patent_app_number] => 838782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3843749 [patent_doc_number] => 05740106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Apparatus and method for nonvolatile configuration circuit' [patent_app_type] => 1 [patent_app_number] => 8/835586 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 6404 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740106.pdf [firstpage_image] =>[orig_patent_app_number] => 835586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152900 [patent_doc_number] => 06061273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Pre-charge step determining circuit of a generic bit line, particularly for non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 8/835347 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5674 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061273.pdf [firstpage_image] =>[orig_patent_app_number] => 835347 [rel_patent_id] =>[rel_patent_doc_number] =>)