
Hieu P. Nguyen
Examiner (ID: 2072, Phone: (571)272-8577 , Office: P/2842 )
| Most Active Art Unit | 2843 |
| Art Unit(s) | 2842, 2843, 2817 |
| Total Applications | 1822 |
| Issued Applications | 1643 |
| Pending Applications | 85 |
| Abandoned Applications | 121 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19532609
[patent_doc_number] => 20240356511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => SWITCHING AMPLIFIER HAVING LINEAR TRANSITION TOTEM POLE MODULATION
[patent_app_type] => utility
[patent_app_number] => 18/761382
[patent_app_country] => US
[patent_app_date] => 2024-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8842
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761382
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/761382 | SWITCHING AMPLIFIER HAVING LINEAR TRANSITION TOTEM POLE MODULATION | Jul 1, 2024 | Pending |
Array
(
[id] => 19544407
[patent_doc_number] => 20240361443
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => RADAR APPARATUS, SYSTEM, AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/759872
[patent_app_country] => US
[patent_app_date] => 2024-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 39997
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759872
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/759872 | RADAR APPARATUS, SYSTEM, AND METHOD | Jun 28, 2024 | Pending |
Array
(
[id] => 19590699
[patent_doc_number] => 20240388256
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => IMPEDANCE CONTROL IN MERGED STACKED FET AMPLIFIERS
[patent_app_type] => utility
[patent_app_number] => 18/622519
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9052
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622519
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/622519 | IMPEDANCE CONTROL IN MERGED STACKED FET AMPLIFIERS | Mar 28, 2024 | Pending |
Array
(
[id] => 20251747
[patent_doc_number] => 20250300616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => SYSTEMS AND METHODS FOR HIGH ACCURACY OPEN LOOP TRANSCONDUCTANCE AMPLIFIER HAVING GAIN SET BY OUTPUT LOAD
[patent_app_type] => utility
[patent_app_number] => 18/609004
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4374
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609004
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609004 | SYSTEMS AND METHODS FOR HIGH ACCURACY OPEN LOOP TRANSCONDUCTANCE AMPLIFIER HAVING GAIN SET BY OUTPUT LOAD | Mar 18, 2024 | Pending |
Array
(
[id] => 19453593
[patent_doc_number] => 20240313723
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/604433
[patent_app_country] => US
[patent_app_date] => 2024-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8730
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604433
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/604433 | SEMICONDUCTOR DEVICE | Mar 12, 2024 | Pending |
Array
(
[id] => 19713380
[patent_doc_number] => 20250023522
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => AMPLIFICATION CIRCUIT, MULTI-STAGE AMPLIFIER AND AMPLIFIER
[patent_app_type] => utility
[patent_app_number] => 18/602326
[patent_app_country] => US
[patent_app_date] => 2024-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7153
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602326
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/602326 | AMPLIFICATION CIRCUIT, MULTI-STAGE AMPLIFIER AND AMPLIFIER | Mar 11, 2024 | Pending |
Array
(
[id] => 19428820
[patent_doc_number] => 12088260
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-09-10
[patent_title] => System and a method for feedback compression through sample combining in digital predistortion
[patent_app_type] => utility
[patent_app_number] => 18/591765
[patent_app_country] => US
[patent_app_date] => 2024-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 7379
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591765
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/591765 | System and a method for feedback compression through sample combining in digital predistortion | Feb 28, 2024 | Issued |
Array
(
[id] => 19836371
[patent_doc_number] => 20250088157
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-13
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/586906
[patent_app_country] => US
[patent_app_date] => 2024-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3307
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586906
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/586906 | SEMICONDUCTOR DEVICE | Feb 25, 2024 | Pending |
Array
(
[id] => 19385466
[patent_doc_number] => 20240275336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => Integrated Circuit Yield Improvement
[patent_app_type] => utility
[patent_app_number] => 18/585622
[patent_app_country] => US
[patent_app_date] => 2024-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6956
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18585622
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/585622 | Integrated Circuit Yield Improvement | Feb 22, 2024 | Pending |
Array
(
[id] => 20704542
[patent_doc_number] => 12627262
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-12
[patent_title] => Generation and synchronization of pulse-width modulated (PWM) waveforms for radio-frequency (RF) applications
[patent_app_type] => utility
[patent_app_number] => 18/443682
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 52
[patent_no_of_words] => 23977
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443682
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/443682 | Generation and synchronization of pulse-width modulated (PWM) waveforms for radio-frequency (RF) applications | Feb 15, 2024 | Issued |
Array
(
[id] => 19222252
[patent_doc_number] => 20240186956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => DOHERTY AMPLIFIER CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/441291
[patent_app_country] => US
[patent_app_date] => 2024-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14121
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441291
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/441291 | DOHERTY AMPLIFIER CIRCUIT | Feb 13, 2024 | Pending |
Array
(
[id] => 19385465
[patent_doc_number] => 20240275335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => METHOD FOR CONTROLLING AN ENVELOPE SHAPE OF AN OUTPUT SIGNAL OUTPUTTED BY A DRIVER OF A WIRELESS TRANSMITTER, AND CORRESPONDING INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/436510
[patent_app_country] => US
[patent_app_date] => 2024-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4157
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436510
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/436510 | METHOD FOR CONTROLLING AN ENVELOPE SHAPE OF AN OUTPUT SIGNAL OUTPUTTED BY A DRIVER OF A WIRELESS TRANSMITTER, AND CORRESPONDING INTEGRATED CIRCUIT | Feb 7, 2024 | Pending |
Array
(
[id] => 19774003
[patent_doc_number] => 20250055429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-13
[patent_title] => METHODS AND APPARATUS TO REJECT CURRENT RIPPLE
[patent_app_type] => utility
[patent_app_number] => 18/428982
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7008
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428982
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/428982 | METHODS AND APPARATUS TO REJECT CURRENT RIPPLE | Jan 30, 2024 | Pending |
Array
(
[id] => 19350014
[patent_doc_number] => 20240258978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => EFFICIENT FRONT-END MODULE STRUCTURE AND MOBILE DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/426485
[patent_app_country] => US
[patent_app_date] => 2024-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6809
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426485
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/426485 | EFFICIENT FRONT-END MODULE STRUCTURE AND MOBILE DEVICE INCLUDING THE SAME | Jan 29, 2024 | Pending |
Array
(
[id] => 19393535
[patent_doc_number] => 20240283405
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => BIAS VOLTAGE GENERATING CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/420711
[patent_app_country] => US
[patent_app_date] => 2024-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4373
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420711
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/420711 | BIAS VOLTAGE GENERATING CIRCUIT | Jan 22, 2024 | Pending |
Array
(
[id] => 21013535
[patent_doc_number] => 12750026
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-09-29
[patent_title] => Tunable effective inductance for multi-gain LNA with inductive source degeneration
[patent_app_type] => utility
[patent_app_number] => 18/418147
[patent_app_country] => US
[patent_app_date] => 2024-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3852
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418147
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/418147 | Tunable Effective Inductance for Multi-Gain LNA with Inductive Source Degeneration | Jan 18, 2024 | Pending |
Array
(
[id] => 20375678
[patent_doc_number] => 12483123
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-25
[patent_title] => Adaptive DC-DC boost converter arrangement
[patent_app_type] => utility
[patent_app_number] => 18/415136
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415136
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/415136 | Adaptive DC-DC boost converter arrangement | Jan 16, 2024 | Issued |
Array
(
[id] => 21013526
[patent_doc_number] => 12750017
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-09-29
[patent_title] => Class-D audio amplifier
[patent_app_type] => utility
[patent_app_number] => 18/412675
[patent_app_country] => US
[patent_app_date] => 2024-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 0
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412675
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/412675 | CLASS-D AUDIO AMPLIFIER | Jan 14, 2024 | Pending |
Array
(
[id] => 20931967
[patent_doc_number] => 12726164
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-09-01
[patent_title] => Amplifier circuit for microphone, microphone circuit and electronic device
[patent_app_type] => utility
[patent_app_number] => 18/406262
[patent_app_country] => US
[patent_app_date] => 2024-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 0
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406262
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/406262 | AMPLIFIER CIRCUIT FOR MICROPHONE, MICROPHONE CIRCUIT AND ELECTRONIC DEVICE | Jan 7, 2024 | Pending |
Array
(
[id] => 19147219
[patent_doc_number] => 20240146272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => Optimized Multi Gain LNA Enabling Low Current and High Linearity Including Highly Linear Active Bypass
[patent_app_type] => utility
[patent_app_number] => 18/406064
[patent_app_country] => US
[patent_app_date] => 2024-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4748
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406064
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/406064 | Optimized Multi Gain LNA Enabling Low Current and High Linearity Including Highly Linear Active Bypass | Jan 4, 2024 | Pending |