Search

Hiren P. Patel

Examiner (ID: 13532, Phone: (571)270-3366 , Office: P/2196 )

Most Active Art Unit
2196
Art Unit(s)
2196, 2191
Total Applications
599
Issued Applications
484
Pending Applications
37
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14107399 [patent_doc_number] => 20190095375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => REPLACING MECHANICAL/MAGNETIC COMPONENTS WITH A SUPERCOMPUTER [patent_app_type] => utility [patent_app_number] => 15/712319 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712319 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/712319
Replacing mechanical/magnetic components with a supercomputer Sep 21, 2017 Issued
Array ( [id] => 12121069 [patent_doc_number] => 20180004654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/704888 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 18121 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704888
Memory controller and memory system including the same Sep 13, 2017 Issued
Array ( [id] => 14825455 [patent_doc_number] => 10409737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Apparatus, system, and method for positionally aware device management bus address assignment [patent_app_type] => utility [patent_app_number] => 15/700031 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6537 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700031 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700031
Apparatus, system, and method for positionally aware device management bus address assignment Sep 7, 2017 Issued
Array ( [id] => 13304551 [patent_doc_number] => 20180203812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => APPLICATION PROCESSOR AND INTEGRATED CIRCUIT INCLUDING INTERRUPT CONTROLLER [patent_app_type] => utility [patent_app_number] => 15/683907 [patent_app_country] => US [patent_app_date] => 2017-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683907
Application processor and integrated circuit including interrupt controller Aug 22, 2017 Issued
Array ( [id] => 13992527 [patent_doc_number] => 20190065421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => DETERMINING TIMEOUT VALUES FOR COMPUTING SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/683347 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15683347 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/683347
Determining timeout values for computing systems Aug 21, 2017 Issued
Array ( [id] => 14735895 [patent_doc_number] => 10387347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Method to locate SAS JBOD cable routing [patent_app_type] => utility [patent_app_number] => 15/681072 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4932 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681072 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681072
Method to locate SAS JBOD cable routing Aug 17, 2017 Issued
Array ( [id] => 15075355 [patent_doc_number] => 10467168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Systems and methods for modular expansion in data storage libraries [patent_app_type] => utility [patent_app_number] => 15/681253 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8830 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681253 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681253
Systems and methods for modular expansion in data storage libraries Aug 17, 2017 Issued
Array ( [id] => 13725851 [patent_doc_number] => 20170373881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SYSTEMS AND METHODS FOR CONTROLLING ISOCHRONOUS DATA STREAMS [patent_app_type] => utility [patent_app_number] => 15/631807 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631807
SYSTEMS AND METHODS FOR CONTROLLING ISOCHRONOUS DATA STREAMS Jun 22, 2017 Abandoned
Array ( [id] => 13738389 [patent_doc_number] => 20180373664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => APPARATUS, SYSTEM, AND METHOD FOR PERFORMING HARDWARE ACCELERATION VIA EXPANSION CARDS [patent_app_type] => utility [patent_app_number] => 15/631861 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631861
Apparatus, system, and method for performing hardware acceleration via expansion cards Jun 22, 2017 Issued
Array ( [id] => 11989184 [patent_doc_number] => 20170293339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'APPARATUS AND METHODS FOR COMMUNICATING POWER AND DATA WITH ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 15/632262 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7623 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632262 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/632262
Apparatus and methods for communicating power and data with electronic devices Jun 22, 2017 Issued
Array ( [id] => 17151011 [patent_doc_number] => 11144085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Dynamic maximum frequency limit for processing core groups [patent_app_type] => utility [patent_app_number] => 15/632000 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8667 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/632000
Dynamic maximum frequency limit for processing core groups Jun 22, 2017 Issued
Array ( [id] => 13627257 [patent_doc_number] => 20180365180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => MANAGEMENT OF DATA TRANSACTION FROM I/O DEVICES [patent_app_type] => utility [patent_app_number] => 15/623429 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623429 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/623429
Management of data transaction from I/O devices Jun 14, 2017 Issued
Array ( [id] => 13595501 [patent_doc_number] => 20180349299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => HARDWARE QUEUE MANAGER WITH WATER MARKING [patent_app_type] => utility [patent_app_number] => 15/609947 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8729 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609947
Hardware queue manager with water marking May 30, 2017 Issued
Array ( [id] => 12173937 [patent_doc_number] => 09892081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Split transaction protocol for a bus system' [patent_app_type] => utility [patent_app_number] => 15/600335 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 9752 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600335
Split transaction protocol for a bus system May 18, 2017 Issued
Array ( [id] => 14523139 [patent_doc_number] => 10338829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Managing multipath configuraton in data center using remote access controller [patent_app_type] => utility [patent_app_number] => 15/588424 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6048 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588424 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/588424
Managing multipath configuraton in data center using remote access controller May 4, 2017 Issued
Array ( [id] => 15425919 [patent_doc_number] => 10545888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Data inversion circuit [patent_app_type] => utility [patent_app_number] => 15/493666 [patent_app_country] => US [patent_app_date] => 2017-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493666
Data inversion circuit Apr 20, 2017 Issued
Array ( [id] => 15075367 [patent_doc_number] => 10467174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => System and method of monitoring data traffic on a MIL-STD-1553 data bus [patent_app_type] => utility [patent_app_number] => 15/493022 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493022 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493022
System and method of monitoring data traffic on a MIL-STD-1553 data bus Apr 19, 2017 Issued
Array ( [id] => 15014723 [patent_doc_number] => 10453517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => High capacity memory system using controller component [patent_app_type] => utility [patent_app_number] => 15/483817 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 76 [patent_no_of_words] => 28135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483817 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483817
High capacity memory system using controller component Apr 9, 2017 Issued
Array ( [id] => 11823916 [patent_doc_number] => 20170212853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/483041 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 16210 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483041
Semiconductor device Apr 9, 2017 Issued
Array ( [id] => 13483083 [patent_doc_number] => 20180293084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => AUTOMATIC LOAD BALANCING FOR RESOURCE ALLOCATIONS [patent_app_type] => utility [patent_app_number] => 15/482415 [patent_app_country] => US [patent_app_date] => 2017-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15482415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/482415
Automatic load balancing for resource allocations Apr 6, 2017 Issued
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