
Hoa B. Trinh
Examiner (ID: 4300, Phone: (571)272-1719 , Office: P/2817 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2817, 2813, 2893, 3731, 2814 |
| Total Applications | 1769 |
| Issued Applications | 1421 |
| Pending Applications | 107 |
| Abandoned Applications | 243 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7750615
[patent_doc_number] => 20120025389
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-02
[patent_title] => 'Hermetic Wafer Level Packaging'
[patent_app_type] => utility
[patent_app_number] => 12/846504
[patent_app_country] => US
[patent_app_date] => 2010-07-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0025/20120025389.pdf
[firstpage_image] =>[orig_patent_app_number] => 12846504
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/846504 | Hermetic wafer level packaging | Jul 28, 2010 | Issued |
Array
(
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[patent_issue_date] => 2012-11-20
[patent_title] => 'Manufacturing method of semiconductor device and semiconductor device'
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Array
(
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[patent_kind] => A1
[patent_issue_date] => 2012-02-02
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE WITH VOLTAGE DISTRIBUTOR'
[patent_app_type] => utility
[patent_app_number] => 12/844922
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[patent_app_date] => 2010-07-28
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[firstpage_image] =>[orig_patent_app_number] => 12844922
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/844922 | Integrated circuit package with voltage distributor | Jul 27, 2010 | Issued |
Array
(
[id] => 7750628
[patent_doc_number] => 20120025396
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-02
[patent_title] => 'SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING'
[patent_app_type] => utility
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[patent_app_country] => US
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Array
(
[id] => 6193159
[patent_doc_number] => 20110024913
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[patent_title] => 'SEMICONDUCTOR DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/844371 | SEMICONDUCTOR DEVICE | Jul 26, 2010 | Abandoned |
Array
(
[id] => 8217446
[patent_doc_number] => 20120133061
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[patent_kind] => A1
[patent_issue_date] => 2012-05-31
[patent_title] => 'PHOTOSENSITIVE ADHESIVE, AND FILM ADHESIVE, ADHESIVE SHEET, ADHESIVE PATTERN, SEMICONDUCTOR WAFER WITH ADHESIVE LAYER, AND SEMICONDUCTOR DEVICE, WHICH ARE MADE USING SAME'
[patent_app_type] => utility
[patent_app_number] => 13/380349
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Array
(
[id] => 8154933
[patent_doc_number] => 20120098147
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-26
[patent_title] => 'PLASMA TREATMENT METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/380843
[patent_app_country] => US
[patent_app_date] => 2010-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => publications/A1/0098/20120098147.pdf
[firstpage_image] =>[orig_patent_app_number] => 13380843
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/380843 | Plasma treatment method | Jun 24, 2010 | Issued |
Array
(
[id] => 8328595
[patent_doc_number] => 08236690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-07
[patent_title] => 'Method for fabricating semiconductor package substrate having different thicknesses between wire bonding pad and ball pad'
[patent_app_type] => utility
[patent_app_number] => 12/801723
[patent_app_country] => US
[patent_app_date] => 2010-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/801723 | Method for fabricating semiconductor package substrate having different thicknesses between wire bonding pad and ball pad | Jun 21, 2010 | Issued |
Array
(
[id] => 6021157
[patent_doc_number] => 20110049483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-03
[patent_title] => 'ORGANIC ELECTROLUMINESCENCE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/816030
[patent_app_country] => US
[patent_app_date] => 2010-06-15
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[firstpage_image] =>[orig_patent_app_number] => 12816030
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/816030 | Organic electroluminescence device | Jun 14, 2010 | Issued |
Array
(
[id] => 8283325
[patent_doc_number] => 08217430
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[patent_issue_date] => 2012-07-10
[patent_title] => 'Power line layout techniques for integrated circuits having modular cells'
[patent_app_type] => utility
[patent_app_number] => 12/786003
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Array
(
[id] => 6461214
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[patent_issue_date] => 2010-08-19
[patent_title] => 'METHOD OF REFINING SOLDER MATERIALS'
[patent_app_type] => utility
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Array
(
[id] => 6483017
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[patent_title] => 'Bonding pad structure, electronic device having a bonding pad structure and methods of fabricating the same'
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Array
(
[id] => 8470325
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Array
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Array
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Array
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Array
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Array
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Array
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