Hoa B. Trinh

Array ( [id] => 10112235 [patent_doc_number] => 09147654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-29 [patent_title] => 'Integrated circuit system employing alternating conductive layers' [patent_app_type] => utility [patent_app_number] => 12/168816 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12168816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5334572 [patent_doc_number] => 20090051036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Semiconductor Package Having Buss-Less Substrate' [patent_app_type] => utility [patent_app_number] => 12/168280 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4381 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20090051036.pdf [firstpage_image] =>[orig_patent_app_number] => 12168280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7987771 [patent_doc_number] => 08076180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Repairable semiconductor device and method' [patent_app_type] => utility [patent_app_number] => 12/168255 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 6743 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/076/08076180.pdf [firstpage_image] =>[orig_patent_app_number] => 12168255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5307549 [patent_doc_number] => 20090014830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/168116 [patent_app_country] => US [patent_app_date] => 2008-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20090014830.pdf [firstpage_image] =>[orig_patent_app_number] => 12168116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6591920 [patent_doc_number] => 20100001402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'Multiple Patterning Method' [patent_app_type] => utility [patent_app_number] => 12/167815 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4350 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20100001402.pdf [firstpage_image] =>[orig_patent_app_number] => 12167815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5293806 [patent_doc_number] => 20090008732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/167766 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3621 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20090008732.pdf [firstpage_image] =>[orig_patent_app_number] => 12167766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4960174 [patent_doc_number] => 20080274599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A TRENCH SURROUNDING PLURAL UNIT CELLS' [patent_app_type] => utility [patent_app_number] => 12/165991 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4523 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20080274599.pdf [firstpage_image] =>[orig_patent_app_number] => 12165991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4597211 [patent_doc_number] => 07982315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Semiconductor structure and method of making the same' [patent_app_type] => utility [patent_app_number] => 12/165587 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2535 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/982/07982315.pdf [firstpage_image] =>[orig_patent_app_number] => 12165587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5346136 [patent_doc_number] => 20090001497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 12/164507 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9136 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001497.pdf [firstpage_image] =>[orig_patent_app_number] => 12164507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5461757 [patent_doc_number] => 20090321957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Layered chip package and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 12/216168 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15701 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20090321957.pdf [firstpage_image] =>[orig_patent_app_number] => 12216168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6240391 [patent_doc_number] => 20100133697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'LOW RESISTANCE THROUGH-WAFER VIA' [patent_app_type] => utility [patent_app_number] => 12/452468 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10516 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20100133697.pdf [firstpage_image] =>[orig_patent_app_number] => 12452468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7775601 [patent_doc_number] => 08120157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Printed wiring board structure, electronic component mounting method and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 12/163877 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3718 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120157.pdf [firstpage_image] =>[orig_patent_app_number] => 12163877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5346247 [patent_doc_number] => 20090001608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Semiconductor device and wire bonding method' [patent_app_type] => utility [patent_app_number] => 12/215317 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7526 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001608.pdf [firstpage_image] =>[orig_patent_app_number] => 12215317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4849648 [patent_doc_number] => 20080315390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Chip Scale Package For A Micro Component' [patent_app_type] => utility [patent_app_number] => 12/143003 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2149 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315390.pdf [firstpage_image] =>[orig_patent_app_number] => 12143003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9692576 [patent_doc_number] => 08823179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Electronic device package and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/667383 [patent_app_country] => US [patent_app_date] => 2008-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 6777 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12667383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5371678 [patent_doc_number] => 20090309238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'Molded flip chip package with enhanced mold-die adhesion' [patent_app_type] => utility [patent_app_number] => 12/157818 [patent_app_country] => US [patent_app_date] => 2008-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2697 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20090309238.pdf [firstpage_image] =>[orig_patent_app_number] => 12157818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4708093 [patent_doc_number] => 20080296619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'ADHESIVE BONDING WITH LOW TEMPERATURE GROWN AMORPHOUS OR POLYCRYSTALLINE COMPOUND SEMICONDUCTORS' [patent_app_type] => utility [patent_app_number] => 12/138167 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11857 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296619.pdf [firstpage_image] =>[orig_patent_app_number] => 12138167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4946994 [patent_doc_number] => 20080303120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Semiconductor chip package' [patent_app_type] => utility [patent_app_number] => 12/155867 [patent_app_country] => US [patent_app_date] => 2008-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4387 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303120.pdf [firstpage_image] =>[orig_patent_app_number] => 12155867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 184902 [patent_doc_number] => 07648846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Active matrix substrate and repairing method thereof' [patent_app_type] => utility [patent_app_number] => 12/129639 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2726 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/648/07648846.pdf [firstpage_image] =>[orig_patent_app_number] => 12129639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4947019 [patent_doc_number] => 20080303145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Printed Circuit Board, Printed Circuit Board Manufacturing Method and Electronic Device' [patent_app_type] => utility [patent_app_number] => 12/128558 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2969 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303145.pdf [firstpage_image] =>[orig_patent_app_number] => 12128558 [rel_patent_id] =>[rel_patent_doc_number] =>)