Search

Hoa B. Trinh

Examiner (ID: 4300, Phone: (571)272-1719 , Office: P/2817 )

Most Active Art Unit
2814
Art Unit(s)
2817, 2813, 2893, 3731, 2814
Total Applications
1769
Issued Applications
1421
Pending Applications
107
Abandoned Applications
243

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 856734 [patent_doc_number] => 07374993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Methods of forming capacitors' [patent_app_type] => utility [patent_app_number] => 10/695959 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2967 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/374/07374993.pdf [firstpage_image] =>[orig_patent_app_number] => 10695959 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695959
Methods of forming capacitors Oct 26, 2003 Issued
Array ( [id] => 681103 [patent_doc_number] => 07084480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Resistive polysilicon element controllable to irreversibly decrease its value' [patent_app_type] => utility [patent_app_number] => 10/694158 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4097 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084480.pdf [firstpage_image] =>[orig_patent_app_number] => 10694158 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/694158
Resistive polysilicon element controllable to irreversibly decrease its value Oct 26, 2003 Issued
Array ( [id] => 7201253 [patent_doc_number] => 20040086792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Lithographic mask for semiconductor devices with a polygonal-section etch window, in particular having a section of at least six sides' [patent_app_type] => new [patent_app_number] => 10/693479 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2812 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20040086792.pdf [firstpage_image] =>[orig_patent_app_number] => 10693479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/693479
Lithographic mask for semiconductor devices with a polygonal-section etch window, in particular having a section of at least six sides Oct 23, 2003 Abandoned
Array ( [id] => 630795 [patent_doc_number] => 07132756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/692938 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 50 [patent_no_of_words] => 19499 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132756.pdf [firstpage_image] =>[orig_patent_app_number] => 10692938 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/692938
Semiconductor device and method for manufacturing the same Oct 23, 2003 Issued
Array ( [id] => 988403 [patent_doc_number] => 06921958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'IGBT with a Schottky barrier diode' [patent_app_type] => utility [patent_app_number] => 10/689058 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4453 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/921/06921958.pdf [firstpage_image] =>[orig_patent_app_number] => 10689058 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/689058
IGBT with a Schottky barrier diode Oct 20, 2003 Issued
Array ( [id] => 142672 [patent_doc_number] => 07687879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Intermediate semiconductor device structure' [patent_app_type] => utility [patent_app_number] => 10/690319 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3929 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/687/07687879.pdf [firstpage_image] =>[orig_patent_app_number] => 10690319 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/690319
Intermediate semiconductor device structure Oct 19, 2003 Issued
Array ( [id] => 889009 [patent_doc_number] => 07348600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Nitride semiconductor device, and its fabrication process' [patent_app_type] => utility [patent_app_number] => 10/687768 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 10328 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/348/07348600.pdf [firstpage_image] =>[orig_patent_app_number] => 10687768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687768
Nitride semiconductor device, and its fabrication process Oct 19, 2003 Issued
Array ( [id] => 7318834 [patent_doc_number] => 20040135177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Semiconductor integrated circuit having a scan test' [patent_app_type] => new [patent_app_number] => 10/687659 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2840 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135177.pdf [firstpage_image] =>[orig_patent_app_number] => 10687659 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687659
Semiconductor integrated circuit having a scan test Oct 19, 2003 Abandoned
Array ( [id] => 7372015 [patent_doc_number] => 20040080041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Semiconductor device with improved heatsink structure' [patent_app_type] => new [patent_app_number] => 10/687999 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2811 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080041.pdf [firstpage_image] =>[orig_patent_app_number] => 10687999 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687999
Semiconductor device with improved heatsink structure Oct 16, 2003 Issued
Array ( [id] => 679626 [patent_doc_number] => 07084010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-01 [patent_title] => 'Integrated package design and method for a radiation sensing device' [patent_app_type] => utility [patent_app_number] => 10/688708 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5310 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084010.pdf [firstpage_image] =>[orig_patent_app_number] => 10688708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688708
Integrated package design and method for a radiation sensing device Oct 16, 2003 Issued
Array ( [id] => 7383014 [patent_doc_number] => 20040082085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method for aligning and exposing a semiconductor wafer' [patent_app_type] => new [patent_app_number] => 10/686848 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3920 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082085.pdf [firstpage_image] =>[orig_patent_app_number] => 10686848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686848
Method for aligning and exposing a semiconductor wafer Oct 15, 2003 Issued
Array ( [id] => 1040918 [patent_doc_number] => 06870217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Method of and apparatus for driving a dual gated MOSFET' [patent_app_type] => utility [patent_app_number] => 10/686859 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2830 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870217.pdf [firstpage_image] =>[orig_patent_app_number] => 10686859 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686859
Method of and apparatus for driving a dual gated MOSFET Oct 15, 2003 Issued
Array ( [id] => 7155265 [patent_doc_number] => 20050082942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Combined power source' [patent_app_type] => utility [patent_app_number] => 10/687030 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2496 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082942.pdf [firstpage_image] =>[orig_patent_app_number] => 10687030 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687030
Combined power source Oct 15, 2003 Abandoned
Array ( [id] => 5790824 [patent_doc_number] => 20060011931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'IC PACKAGE WITH AN INTEGRATED POWER SOURCE' [patent_app_type] => utility [patent_app_number] => 10/685249 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3022 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20060011931.pdf [firstpage_image] =>[orig_patent_app_number] => 10685249 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/685249
IC package with an integrated power source Oct 13, 2003 Issued
Array ( [id] => 637781 [patent_doc_number] => 07125743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Method for reduction of electromagnetic interference in integrated circuit packages' [patent_app_type] => utility [patent_app_number] => 10/684072 [patent_app_country] => US [patent_app_date] => 2003-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2916 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/125/07125743.pdf [firstpage_image] =>[orig_patent_app_number] => 10684072 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/684072
Method for reduction of electromagnetic interference in integrated circuit packages Oct 12, 2003 Issued
Array ( [id] => 982599 [patent_doc_number] => 06927443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/682479 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5147 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927443.pdf [firstpage_image] =>[orig_patent_app_number] => 10682479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682479
Nonvolatile semiconductor memory device Oct 9, 2003 Issued
Array ( [id] => 476621 [patent_doc_number] => 07227242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-05 [patent_title] => 'Structure and method for enhanced performance in semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 10/683719 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2213 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227242.pdf [firstpage_image] =>[orig_patent_app_number] => 10683719 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/683719
Structure and method for enhanced performance in semiconductor substrates Oct 8, 2003 Issued
Array ( [id] => 7220541 [patent_doc_number] => 20050077603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Method and structure for a wafer level packaging' [patent_app_type] => utility [patent_app_number] => 10/680434 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4893 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077603.pdf [firstpage_image] =>[orig_patent_app_number] => 10680434 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/680434
Method and structure for a wafer level packaging Oct 7, 2003 Abandoned
Array ( [id] => 7252810 [patent_doc_number] => 20050074927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Adhesive bonding with low temperature grown amorphous or polycrystalline compound semiconductors' [patent_app_type] => utility [patent_app_number] => 10/680509 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11809 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20050074927.pdf [firstpage_image] =>[orig_patent_app_number] => 10680509 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/680509
Adhesive bonding with low temperature grown amorphous or polycrystalline compound semiconductors Oct 6, 2003 Issued
Array ( [id] => 5110496 [patent_doc_number] => 20070194411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Thermal Treatment Apparatus, Method For Manufacturing Semiconductor Device, And Method For Manufacturing Substrate' [patent_app_type] => utility [patent_app_number] => 10/528069 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10368 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194411.pdf [firstpage_image] =>[orig_patent_app_number] => 10528069 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/528069
Thermal treatment apparatus, method for manufacturing semiconductor device, and method for manufacturing substrate Sep 25, 2003 Issued
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