Hoa B. Trinh

Array ( [id] => 1106299 [patent_doc_number] => 06812567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Semiconductor package and package stack made thereof' [patent_app_type] => B2 [patent_app_number] => 10/660539 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2301 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812567.pdf [firstpage_image] =>[orig_patent_app_number] => 10660539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 996877 [patent_doc_number] => 06914319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Semiconductor device having a fuse' [patent_app_type] => utility [patent_app_number] => 10/660168 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 3298 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914319.pdf [firstpage_image] =>[orig_patent_app_number] => 10660168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 757589 [patent_doc_number] => 07015078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-21 [patent_title] => 'Silicon on insulator substrate having improved thermal conductivity and method of its formation' [patent_app_type] => utility [patent_app_number] => 10/658668 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4844 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015078.pdf [firstpage_image] =>[orig_patent_app_number] => 10658668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 760877 [patent_doc_number] => 07012007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-14 [patent_title] => 'Strained silicon MOSFET having improved thermal conductivity and method for its fabrication' [patent_app_type] => utility [patent_app_number] => 10/658479 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4373 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012007.pdf [firstpage_image] =>[orig_patent_app_number] => 10658479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7343346 [patent_doc_number] => 20040046236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Semiconductor package method' [patent_app_type] => new [patent_app_number] => 10/655869 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20040046236.pdf [firstpage_image] =>[orig_patent_app_number] => 10655869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 473984 [patent_doc_number] => 07230291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Ferroelectric capacitors having oxidation barrier conductive layers and lower electrodes disposed in trenches defined by supporting insulating layers' [patent_app_type] => utility [patent_app_number] => 10/650879 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 7554 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230291.pdf [firstpage_image] =>[orig_patent_app_number] => 10650879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7191301 [patent_doc_number] => 20050040459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Method and structure for improving the gate resistance of a closed cell trench power MOSFET' [patent_app_type] => utility [patent_app_number] => 10/647029 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3650 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20050040459.pdf [firstpage_image] =>[orig_patent_app_number] => 10647029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7609889 [patent_doc_number] => 06998298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-14 [patent_title] => 'Thyristor semiconductor memory device and method of manufacture' [patent_app_type] => utility [patent_app_number] => 10/639058 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 11926 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998298.pdf [firstpage_image] =>[orig_patent_app_number] => 10639058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7206468 [patent_doc_number] => 20050258537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/632709 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20050258537.pdf [firstpage_image] =>[orig_patent_app_number] => 10632709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7386560 [patent_doc_number] => 20040021172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same' [patent_app_type] => new [patent_app_number] => 10/631199 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3903 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20040021172.pdf [firstpage_image] =>[orig_patent_app_number] => 10631199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7400633 [patent_doc_number] => 20040023465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Memory cell capacitors having an over/under configuration' [patent_app_type] => new [patent_app_number] => 10/631555 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7090 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023465.pdf [firstpage_image] =>[orig_patent_app_number] => 10631555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7398896 [patent_doc_number] => 20040018698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Adjustable threshold isolation transistor' [patent_app_type] => new [patent_app_number] => 10/630598 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20040018698.pdf [firstpage_image] =>[orig_patent_app_number] => 10630598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7022968 [patent_doc_number] => 20050017362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Low gate resistance layout procedure for RF transistor devices' [patent_app_type] => utility [patent_app_number] => 10/627289 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3024 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017362.pdf [firstpage_image] =>[orig_patent_app_number] => 10627289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1037470 [patent_doc_number] => 06872619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Semiconductor device having trench top isolation layer and method for forming the same' [patent_app_type] => utility [patent_app_number] => 10/620869 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2626 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872619.pdf [firstpage_image] =>[orig_patent_app_number] => 10620869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 687738 [patent_doc_number] => 07078749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-18 [patent_title] => 'Memory structure having tunable interlayer dielectric and method for fabricating same' [patent_app_type] => utility [patent_app_number] => 10/618156 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2973 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078749.pdf [firstpage_image] =>[orig_patent_app_number] => 10618156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1120804 [patent_doc_number] => 06797997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => B2 [patent_app_number] => 10/609478 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797997.pdf [firstpage_image] =>[orig_patent_app_number] => 10609478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7405178 [patent_doc_number] => 20040262750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Underfill and mold compounds including siloxane-based aromatic diamines' [patent_app_type] => new [patent_app_number] => 10/611618 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262750.pdf [firstpage_image] =>[orig_patent_app_number] => 10611618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1031473 [patent_doc_number] => 06879019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Guard ring of a combination wafer or singulated die' [patent_app_type] => utility [patent_app_number] => 10/603629 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2408 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/879/06879019.pdf [firstpage_image] =>[orig_patent_app_number] => 10603629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7611051 [patent_doc_number] => 06841806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Heterojunction thyristor-based amplifier' [patent_app_type] => utility [patent_app_number] => 10/602218 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11741 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841806.pdf [firstpage_image] =>[orig_patent_app_number] => 10602218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6823742 [patent_doc_number] => 20030234363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Component of a radiation detector, radiation detector and radiation detection apparatus' [patent_app_type] => new [patent_app_number] => 10/600595 [patent_app_country] => US [patent_app_date] => 2003-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14031 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20030234363.pdf [firstpage_image] =>[orig_patent_app_number] => 10600595 [rel_patent_id] =>[rel_patent_doc_number] =>)