Search

Hoa T. Nguyen

Examiner (ID: 2558)

Most Active Art Unit
2313
Art Unit(s)
2651, 2627, 2309, 2313, 2305, 2413, 2784, 2652, 2686, 2899, 2785
Total Applications
1071
Issued Applications
702
Pending Applications
26
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3790633 [patent_doc_number] => 05809037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Integrated circuit testing' [patent_app_type] => 1 [patent_app_number] => 8/781051 [patent_app_country] => US [patent_app_date] => 1997-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4229 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809037.pdf [firstpage_image] =>[orig_patent_app_number] => 781051 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781051
Integrated circuit testing Jan 8, 1997 Issued
Array ( [id] => 4124689 [patent_doc_number] => 06101623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Current reduction circuit for testing purpose' [patent_app_type] => 1 [patent_app_number] => 8/779892 [patent_app_country] => US [patent_app_date] => 1997-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 10841 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101623.pdf [firstpage_image] =>[orig_patent_app_number] => 779892 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779892
Current reduction circuit for testing purpose Jan 6, 1997 Issued
Array ( [id] => 4212128 [patent_doc_number] => 06044485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Transmitter method and transmission system using adaptive coding based on channel characteristics' [patent_app_type] => 1 [patent_app_number] => 8/789093 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2557 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044485.pdf [firstpage_image] =>[orig_patent_app_number] => 789093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789093
Transmitter method and transmission system using adaptive coding based on channel characteristics Jan 2, 1997 Issued
Array ( [id] => 3808827 [patent_doc_number] => 05781557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Memory test mode for wordline resistive defects' [patent_app_type] => 1 [patent_app_number] => 8/775574 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4354 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781557.pdf [firstpage_image] =>[orig_patent_app_number] => 775574 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775574
Memory test mode for wordline resistive defects Dec 30, 1996 Issued
Array ( [id] => 3983568 [patent_doc_number] => 05887128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Method and apparatus for redundant disk storage system with offset' [patent_app_type] => 1 [patent_app_number] => 8/775060 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7215 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887128.pdf [firstpage_image] =>[orig_patent_app_number] => 775060 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775060
Method and apparatus for redundant disk storage system with offset Dec 26, 1996 Issued
Array ( [id] => 3854682 [patent_doc_number] => 05848075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Test device employing scan path having circuitry at switches between a scan in signal transmitted and previously held at a predetermined clock timing' [patent_app_type] => 1 [patent_app_number] => 8/772850 [patent_app_country] => US [patent_app_date] => 1996-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3160 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848075.pdf [firstpage_image] =>[orig_patent_app_number] => 772850 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/772850
Test device employing scan path having circuitry at switches between a scan in signal transmitted and previously held at a predetermined clock timing Dec 23, 1996 Issued
Array ( [id] => 3891078 [patent_doc_number] => 05729551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Space efficient column decoder for flash memory redundant columns' [patent_app_type] => 1 [patent_app_number] => 8/768914 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5193 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729551.pdf [firstpage_image] =>[orig_patent_app_number] => 768914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768914
Space efficient column decoder for flash memory redundant columns Dec 16, 1996 Issued
Array ( [id] => 3822484 [patent_doc_number] => 05831991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Methods and apparatus for electrically verifying a functional unit contained within an integrated cirucuit' [patent_app_type] => 1 [patent_app_number] => 8/763371 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831991.pdf [firstpage_image] =>[orig_patent_app_number] => 763371 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763371
Methods and apparatus for electrically verifying a functional unit contained within an integrated cirucuit Dec 12, 1996 Issued
Array ( [id] => 4161273 [patent_doc_number] => 06061815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Programming utility register to generate addresses in algorithmic pattern generator' [patent_app_type] => 1 [patent_app_number] => 8/762611 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3180 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061815.pdf [firstpage_image] =>[orig_patent_app_number] => 762611 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/762611
Programming utility register to generate addresses in algorithmic pattern generator Dec 8, 1996 Issued
Array ( [id] => 3791842 [patent_doc_number] => 05757818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Method and apparatus for scan out testing of integrated circuits with reduced test circuit area' [patent_app_type] => 1 [patent_app_number] => 8/756682 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2278 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757818.pdf [firstpage_image] =>[orig_patent_app_number] => 756682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756682
Method and apparatus for scan out testing of integrated circuits with reduced test circuit area Nov 25, 1996 Issued
Array ( [id] => 3803684 [patent_doc_number] => 05841783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Fail address analysis and repair system for semiconductor test' [patent_app_type] => 1 [patent_app_number] => 8/754922 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1882 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841783.pdf [firstpage_image] =>[orig_patent_app_number] => 754922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/754922
Fail address analysis and repair system for semiconductor test Nov 21, 1996 Issued
Array ( [id] => 3874653 [patent_doc_number] => 05796753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'High speed test pattern transfer apparatus for semiconductor test system' [patent_app_type] => 1 [patent_app_number] => 8/700451 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2994 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796753.pdf [firstpage_image] =>[orig_patent_app_number] => 700451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/700451
High speed test pattern transfer apparatus for semiconductor test system Nov 17, 1996 Issued
Array ( [id] => 3951942 [patent_doc_number] => 05930271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Circuit testing apparatus for testing circuit device including functional block' [patent_app_type] => 1 [patent_app_number] => 8/737522 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7545 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930271.pdf [firstpage_image] =>[orig_patent_app_number] => 737522 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/737522
Circuit testing apparatus for testing circuit device including functional block Nov 11, 1996 Issued
Array ( [id] => 3803747 [patent_doc_number] => 05841788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Methods for backplane interconnect testing' [patent_app_type] => 1 [patent_app_number] => 8/733592 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4095 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841788.pdf [firstpage_image] =>[orig_patent_app_number] => 733592 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733592
Methods for backplane interconnect testing Oct 17, 1996 Issued
Array ( [id] => 3995315 [patent_doc_number] => RE036417 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of detecting changes to a collection of digital signals' [patent_app_type] => 2 [patent_app_number] => 8/732188 [patent_app_country] => US [patent_app_date] => 1996-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5032 [patent_no_of_claims] => 117 [patent_no_of_ind_claims] => 85 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036417.pdf [firstpage_image] =>[orig_patent_app_number] => 732188 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/732188
Method of detecting changes to a collection of digital signals Oct 16, 1996 Issued
Array ( [id] => 3754568 [patent_doc_number] => 05754557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller' [patent_app_type] => 1 [patent_app_number] => 8/720960 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754557.pdf [firstpage_image] =>[orig_patent_app_number] => 720960 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/720960
Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller Oct 9, 1996 Issued
Array ( [id] => 3757850 [patent_doc_number] => 05802070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Testing associative memory' [patent_app_type] => 1 [patent_app_number] => 8/725390 [patent_app_country] => US [patent_app_date] => 1996-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3225 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802070.pdf [firstpage_image] =>[orig_patent_app_number] => 725390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725390
Testing associative memory Oct 2, 1996 Issued
Array ( [id] => 3707418 [patent_doc_number] => 05677916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Semiconductor integrated circuit and its application device' [patent_app_type] => 1 [patent_app_number] => 8/724821 [patent_app_country] => US [patent_app_date] => 1996-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6451 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677916.pdf [firstpage_image] =>[orig_patent_app_number] => 724821 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724821
Semiconductor integrated circuit and its application device Oct 1, 1996 Issued
Array ( [id] => 3826807 [patent_doc_number] => 05771242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/721601 [patent_app_country] => US [patent_app_date] => 1996-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5217 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771242.pdf [firstpage_image] =>[orig_patent_app_number] => 721601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721601
Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor Sep 24, 1996 Issued
Array ( [id] => 3874666 [patent_doc_number] => 05796754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Apparatus for testing digital signal processor in optical disk player' [patent_app_type] => 1 [patent_app_number] => 8/717151 [patent_app_country] => US [patent_app_date] => 1996-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1621 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796754.pdf [firstpage_image] =>[orig_patent_app_number] => 717151 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/717151
Apparatus for testing digital signal processor in optical disk player Sep 19, 1996 Issued
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