Search

Hoa Van Le

Examiner (ID: 13440, Phone: (571)272-1332 , Office: P/1721 )

Most Active Art Unit
1752
Art Unit(s)
1105, 1113, 1507, 1506, 1721, 1724, 1737, 1752, 1795
Total Applications
3483
Issued Applications
2664
Pending Applications
54
Abandoned Applications
766

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4358910 [patent_doc_number] => 06285598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Precision programming of nonvolatile memory cells' [patent_app_type] => 1 [patent_app_number] => 9/523828 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8010 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285598.pdf [firstpage_image] =>[orig_patent_app_number] => 523828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523828
Precision programming of nonvolatile memory cells Mar 12, 2000 Issued
Array ( [id] => 4418824 [patent_doc_number] => 06240026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Bit line sense circuit and method for dynamic random access memories' [patent_app_type] => 1 [patent_app_number] => 9/519714 [patent_app_country] => US [patent_app_date] => 2000-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3876 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240026.pdf [firstpage_image] =>[orig_patent_app_number] => 519714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/519714
Bit line sense circuit and method for dynamic random access memories Mar 6, 2000 Issued
Array ( [id] => 1437714 [patent_doc_number] => 06356503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Reduced latency row selection circuit and method' [patent_app_type] => B1 [patent_app_number] => 09/510692 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356503.pdf [firstpage_image] =>[orig_patent_app_number] => 09510692 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510692
Reduced latency row selection circuit and method Feb 22, 2000 Issued
Array ( [id] => 4262770 [patent_doc_number] => 06222769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Nonvolatile semiconductor storage device having buried electrode within shallow trench' [patent_app_type] => 1 [patent_app_number] => 9/503459 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 73 [patent_no_of_words] => 11033 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222769.pdf [firstpage_image] =>[orig_patent_app_number] => 503459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503459
Nonvolatile semiconductor storage device having buried electrode within shallow trench Feb 13, 2000 Issued
Array ( [id] => 4425624 [patent_doc_number] => 06195304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Semiconductor memory device and its refresh address signal generating method adapted to reduce power consumption during refresh operation' [patent_app_type] => 1 [patent_app_number] => 9/500814 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5492 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195304.pdf [firstpage_image] =>[orig_patent_app_number] => 500814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/500814
Semiconductor memory device and its refresh address signal generating method adapted to reduce power consumption during refresh operation Feb 9, 2000 Issued
Array ( [id] => 4344549 [patent_doc_number] => 06314015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Semiconductor memory device for reading information in memory cells' [patent_app_type] => 1 [patent_app_number] => 9/501710 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6670 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314015.pdf [firstpage_image] =>[orig_patent_app_number] => 501710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501710
Semiconductor memory device for reading information in memory cells Feb 9, 2000 Issued
Array ( [id] => 4419104 [patent_doc_number] => 06301154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor memory device having floating gate type transistors programmed to have differing threshold voltages' [patent_app_type] => 1 [patent_app_number] => 9/497318 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 11355 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301154.pdf [firstpage_image] =>[orig_patent_app_number] => 497318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497318
Semiconductor memory device having floating gate type transistors programmed to have differing threshold voltages Feb 2, 2000 Issued
Array ( [id] => 4418632 [patent_doc_number] => 06240009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Asymmetric ram cell' [patent_app_type] => 1 [patent_app_number] => 9/496714 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4654 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240009.pdf [firstpage_image] =>[orig_patent_app_number] => 496714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496714
Asymmetric ram cell Feb 1, 2000 Issued
Array ( [id] => 1552259 [patent_doc_number] => 06347054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method of operating flash memory' [patent_app_type] => B1 [patent_app_number] => 09/496293 [patent_app_country] => US [patent_app_date] => 2000-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 33 [patent_no_of_words] => 7064 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347054.pdf [firstpage_image] =>[orig_patent_app_number] => 09496293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496293
Method of operating flash memory Jan 31, 2000 Issued
Array ( [id] => 4358761 [patent_doc_number] => 06285588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells' [patent_app_type] => 1 [patent_app_number] => 9/495216 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4194 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285588.pdf [firstpage_image] =>[orig_patent_app_number] => 495216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495216
Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells Jan 30, 2000 Issued
Array ( [id] => 4262800 [patent_doc_number] => 06222771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Unified program method and circuitry in flash EEPROM' [patent_app_type] => 1 [patent_app_number] => 9/494456 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4898 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222771.pdf [firstpage_image] =>[orig_patent_app_number] => 494456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494456
Unified program method and circuitry in flash EEPROM Jan 30, 2000 Issued
Array ( [id] => 4418705 [patent_doc_number] => 06240016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method to reduce read gate disturb for flash EEPROM application' [patent_app_type] => 1 [patent_app_number] => 9/495214 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2827 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240016.pdf [firstpage_image] =>[orig_patent_app_number] => 495214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495214
Method to reduce read gate disturb for flash EEPROM application Jan 30, 2000 Issued
Array ( [id] => 4327200 [patent_doc_number] => 06243287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Distributed decode system and method for improving static random access memory (SRAM) density' [patent_app_type] => 1 [patent_app_number] => 9/492510 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6556 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243287.pdf [firstpage_image] =>[orig_patent_app_number] => 492510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492510
Distributed decode system and method for improving static random access memory (SRAM) density Jan 26, 2000 Issued
Array ( [id] => 4273135 [patent_doc_number] => 06205085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method and circuit for sending a signal in a semiconductor device during a setup time' [patent_app_type] => 1 [patent_app_number] => 9/490803 [patent_app_country] => US [patent_app_date] => 2000-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205085.pdf [firstpage_image] =>[orig_patent_app_number] => 490803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/490803
Method and circuit for sending a signal in a semiconductor device during a setup time Jan 25, 2000 Issued
Array ( [id] => 4369647 [patent_doc_number] => 06219298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'High-speed address decoders and related address decoding methods' [patent_app_type] => 1 [patent_app_number] => 9/487965 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3465 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219298.pdf [firstpage_image] =>[orig_patent_app_number] => 487965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487965
High-speed address decoders and related address decoding methods Jan 17, 2000 Issued
Array ( [id] => 4369582 [patent_doc_number] => 06219294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories' [patent_app_type] => 1 [patent_app_number] => 9/482575 [patent_app_country] => US [patent_app_date] => 2000-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7029 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219294.pdf [firstpage_image] =>[orig_patent_app_number] => 482575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/482575
Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories Jan 12, 2000 Issued
Array ( [id] => 4418892 [patent_doc_number] => 06240033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Antifuse circuitry for post-package DRAM repair' [patent_app_type] => 1 [patent_app_number] => 9/479665 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6152 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240033.pdf [firstpage_image] =>[orig_patent_app_number] => 479665 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479665
Antifuse circuitry for post-package DRAM repair Jan 9, 2000 Issued
Array ( [id] => 4285154 [patent_doc_number] => 06246633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Semiconductor memory device permitting stabilized operation and high-speed access' [patent_app_type] => 1 [patent_app_number] => 9/477559 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8548 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246633.pdf [firstpage_image] =>[orig_patent_app_number] => 477559 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477559
Semiconductor memory device permitting stabilized operation and high-speed access Jan 3, 2000 Issued
Array ( [id] => 4419968 [patent_doc_number] => 06229733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide' [patent_app_type] => 1 [patent_app_number] => 9/475814 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3740 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229733.pdf [firstpage_image] =>[orig_patent_app_number] => 475814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475814
Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide Dec 29, 1999 Issued
Array ( [id] => 4368505 [patent_doc_number] => 06175528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Redundancy circuit and repair method for semiconductor memory device by utilizing ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 9/475280 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 6091 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175528.pdf [firstpage_image] =>[orig_patent_app_number] => 475280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475280
Redundancy circuit and repair method for semiconductor memory device by utilizing ferroelectric memory Dec 29, 1999 Issued
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