Hoa Van Le

Array ( [id] => 4417318 [patent_doc_number] => 06172901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Low power static random access memory and method for writing to same' [patent_app_type] => 1 [patent_app_number] => 9/475318 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4296 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172901.pdf [firstpage_image] =>[orig_patent_app_number] => 475318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374027 [patent_doc_number] => 06256237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor device and method for repairing failed memory cell by directly programming fuse memory cell' [patent_app_type] => 1 [patent_app_number] => 9/473083 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3391 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256237.pdf [firstpage_image] =>[orig_patent_app_number] => 473083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317667 [patent_doc_number] => 06327182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Semiconductor device and a method of operation the same' [patent_app_type] => 1 [patent_app_number] => 9/472920 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5739 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327182.pdf [firstpage_image] =>[orig_patent_app_number] => 472920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419371 [patent_doc_number] => 06301174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Power conservation during memory read operations' [patent_app_type] => 1 [patent_app_number] => 9/470679 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2623 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301174.pdf [firstpage_image] =>[orig_patent_app_number] => 470679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202249 [patent_doc_number] => 06154397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Semiconductor memory device having stabilization circuit for stable signal transmission' [patent_app_type] => 1 [patent_app_number] => 9/471518 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2142 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154397.pdf [firstpage_image] =>[orig_patent_app_number] => 471518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4284850 [patent_doc_number] => 06246614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Clock synchronous semiconductor memory device having a reduced access time' [patent_app_type] => 1 [patent_app_number] => 9/467914 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 44 [patent_no_of_words] => 23523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246614.pdf [firstpage_image] =>[orig_patent_app_number] => 467914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420096 [patent_doc_number] => 06229747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Self-refresh apparatus for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/468784 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2730 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229747.pdf [firstpage_image] =>[orig_patent_app_number] => 468784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420036 [patent_doc_number] => 06229740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Voltage generation circuit having boost function and capable of preventing output voltage from exceeding prescribed value, and semiconductor memory device provided therewith' [patent_app_type] => 1 [patent_app_number] => 9/466481 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5867 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229740.pdf [firstpage_image] =>[orig_patent_app_number] => 466481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4344534 [patent_doc_number] => 06314014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Programmable resistance memory arrays with reference cells' [patent_app_type] => 1 [patent_app_number] => 9/464898 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 13613 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314014.pdf [firstpage_image] =>[orig_patent_app_number] => 464898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1499153 [patent_doc_number] => 06404661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor storage device having arrangement for controlling activation of sense amplifiers' [patent_app_type] => B2 [patent_app_number] => 09/464793 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 55 [patent_no_of_words] => 20857 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404661.pdf [firstpage_image] =>[orig_patent_app_number] => 09464793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317959 [patent_doc_number] => 06252794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'DRAM and data access method for DRAM' [patent_app_type] => 1 [patent_app_number] => 9/464912 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2736 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252794.pdf [firstpage_image] =>[orig_patent_app_number] => 464912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368208 [patent_doc_number] => 06201760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Apparatus and method for performing data read operation in DDR SDRAM' [patent_app_type] => 1 [patent_app_number] => 9/461718 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201760.pdf [firstpage_image] =>[orig_patent_app_number] => 461718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1461131 [patent_doc_number] => 06426901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Logic consolidated semiconductor memory device having memory circuit and logic circuit integrated in the same chip' [patent_app_type] => B2 [patent_app_number] => 09/461298 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5120 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426901.pdf [firstpage_image] =>[orig_patent_app_number] => 09461298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1552279 [patent_doc_number] => 06347057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Semiconductor memory device with sense amplifier block' [patent_app_type] => B1 [patent_app_number] => 09/461285 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13713 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347057.pdf [firstpage_image] =>[orig_patent_app_number] => 09461285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4327540 [patent_doc_number] => 06243307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Semiconductor device including tester circuit suppressible of circuit scale increase and testing device of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/459710 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14952 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243307.pdf [firstpage_image] =>[orig_patent_app_number] => 459710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416942 [patent_doc_number] => 06233186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Memory device having reduced precharge time' [patent_app_type] => 1 [patent_app_number] => 9/457579 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3849 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233186.pdf [firstpage_image] =>[orig_patent_app_number] => 457579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4196985 [patent_doc_number] => 06160735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Negative voltage level shifter circuit and nonviolatile semiconductor storage device including the circuit' [patent_app_type] => 1 [patent_app_number] => 9/455810 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6949 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160735.pdf [firstpage_image] =>[orig_patent_app_number] => 455810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1410403 [patent_doc_number] => 06545919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor memory and output signal control method and circuit in semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/452718 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6053 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545919.pdf [firstpage_image] =>[orig_patent_app_number] => 09452718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318238 [patent_doc_number] => 06327214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Multi-bank memory device having input and output amplifier shared by adjacent memory banks' [patent_app_type] => 1 [patent_app_number] => 9/449110 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3064 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327214.pdf [firstpage_image] =>[orig_patent_app_number] => 449110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261807 [patent_doc_number] => 06137731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor memory including an intermediate potential circuit capable of providing reduced current flow' [patent_app_type] => 1 [patent_app_number] => 9/447212 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6639 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137731.pdf [firstpage_image] =>[orig_patent_app_number] => 447212 [rel_patent_id] =>[rel_patent_doc_number] =>)