Hoa Van Le

Array ( [id] => 4309943 [patent_doc_number] => 06185150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Clock-synchronous system' [patent_app_type] => 1 [patent_app_number] => 9/448412 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4026 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185150.pdf [firstpage_image] =>[orig_patent_app_number] => 448412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110746 [patent_doc_number] => 06097667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Synchronous memory with programmable read latency' [patent_app_type] => 1 [patent_app_number] => 9/443874 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6074 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097667.pdf [firstpage_image] =>[orig_patent_app_number] => 443874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261496 [patent_doc_number] => 06137712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Ferroelectric memory configuration' [patent_app_type] => 1 [patent_app_number] => 9/440818 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3770 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137712.pdf [firstpage_image] =>[orig_patent_app_number] => 440818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4367694 [patent_doc_number] => 06201724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Semiconductor memory having improved register array access speed' [patent_app_type] => 1 [patent_app_number] => 9/437010 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201724.pdf [firstpage_image] =>[orig_patent_app_number] => 437010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368343 [patent_doc_number] => 06175517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Insertble and removable digital memory apparatus' [patent_app_type] => 1 [patent_app_number] => 9/435495 [patent_app_country] => US [patent_app_date] => 1999-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 11816 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175517.pdf [firstpage_image] =>[orig_patent_app_number] => 435495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4308955 [patent_doc_number] => 06181598 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Data line disturbance free memory block divided flash memory and microcomputer having flash memory' [patent_app_type] => 1 [patent_app_number] => 9/435037 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 79 [patent_no_of_words] => 31534 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181598.pdf [firstpage_image] =>[orig_patent_app_number] => 435037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425559 [patent_doc_number] => 06178120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Memory structure for speeding up data access' [patent_app_type] => 1 [patent_app_number] => 9/431218 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2560 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178120.pdf [firstpage_image] =>[orig_patent_app_number] => 431218 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309098 [patent_doc_number] => 06181606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Nonvolatile integrated circuit memory devices having improved word line driving capability and methods of operating same' [patent_app_type] => 1 [patent_app_number] => 9/428816 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4772 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181606.pdf [firstpage_image] =>[orig_patent_app_number] => 428816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1590021 [patent_doc_number] => 06359825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Dynamic memory with increased access speed and reduced chip area' [patent_app_type] => B1 [patent_app_number] => 09/428712 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4167 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359825.pdf [firstpage_image] =>[orig_patent_app_number] => 09428712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425512 [patent_doc_number] => 06178107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Ferroelectric random access memory device capable of reducing operation frequency of reference cell' [patent_app_type] => 1 [patent_app_number] => 9/428110 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1289 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178107.pdf [firstpage_image] =>[orig_patent_app_number] => 428110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363748 [patent_doc_number] => 06215713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Bitline amplifier having improved response' [patent_app_type] => 1 [patent_app_number] => 9/426446 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5072 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215713.pdf [firstpage_image] =>[orig_patent_app_number] => 426446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147859 [patent_doc_number] => 06122201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM' [patent_app_type] => 1 [patent_app_number] => 9/421516 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2882 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122201.pdf [firstpage_image] =>[orig_patent_app_number] => 421516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380980 [patent_doc_number] => 06275426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Row redundancy for content addressable memory' [patent_app_type] => 1 [patent_app_number] => 9/420516 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7658 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275426.pdf [firstpage_image] =>[orig_patent_app_number] => 420516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202013 [patent_doc_number] => 06130836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Semiconductor IC device having a control register for designating memory blocks for erasure' [patent_app_type] => 1 [patent_app_number] => 9/414170 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 80 [patent_no_of_words] => 31529 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130836.pdf [firstpage_image] =>[orig_patent_app_number] => 414170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252068 [patent_doc_number] => 06166953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein' [patent_app_type] => 1 [patent_app_number] => 9/414944 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 80 [patent_no_of_words] => 31533 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166953.pdf [firstpage_image] =>[orig_patent_app_number] => 414944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407091 [patent_doc_number] => 06297990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Balanced reference sensing circuit' [patent_app_type] => 1 [patent_app_number] => 9/407216 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3426 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297990.pdf [firstpage_image] =>[orig_patent_app_number] => 407216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425600 [patent_doc_number] => 06178138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Asynchronously addressable clocked memory device and method of operating same' [patent_app_type] => 1 [patent_app_number] => 9/400212 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4852 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178138.pdf [firstpage_image] =>[orig_patent_app_number] => 400212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247408 [patent_doc_number] => 06118712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Redundancy fuse boxes and redundancy repair structures for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/395543 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6156 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118712.pdf [firstpage_image] =>[orig_patent_app_number] => 395543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363337 [patent_doc_number] => 06215686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Memory system with switching for data isolation' [patent_app_type] => 1 [patent_app_number] => 9/384471 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 22 [patent_no_of_words] => 7009 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215686.pdf [firstpage_image] =>[orig_patent_app_number] => 384471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4367945 [patent_doc_number] => 06201741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Storage device and a control method of the storage device' [patent_app_type] => 1 [patent_app_number] => 9/383512 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 10293 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201741.pdf [firstpage_image] =>[orig_patent_app_number] => 383512 [rel_patent_id] =>[rel_patent_doc_number] =>)