
Hoa Van Le
Examiner (ID: 13440, Phone: (571)272-1332 , Office: P/1721 )
| Most Active Art Unit | 1752 |
| Art Unit(s) | 1105, 1113, 1507, 1506, 1721, 1724, 1737, 1752, 1795 |
| Total Applications | 3483 |
| Issued Applications | 2664 |
| Pending Applications | 54 |
| Abandoned Applications | 766 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4197269
[patent_doc_number] => 06094385
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Repairable memory cell for a memory cell array'
[patent_app_type] => 1
[patent_app_number] => 9/371492
[patent_app_country] => US
[patent_app_date] => 1999-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5987
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/094/06094385.pdf
[firstpage_image] =>[orig_patent_app_number] => 371492
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/371492 | Repairable memory cell for a memory cell array | Aug 9, 1999 | Issued |
Array
(
[id] => 4093643
[patent_doc_number] => 06055202
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Multi-bank architecture for a wide I/O DRAM'
[patent_app_type] => 1
[patent_app_number] => 9/365819
[patent_app_country] => US
[patent_app_date] => 1999-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3106
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/055/06055202.pdf
[firstpage_image] =>[orig_patent_app_number] => 365819
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/365819 | Multi-bank architecture for a wide I/O DRAM | Aug 2, 1999 | Issued |
Array
(
[id] => 1600137
[patent_doc_number] => 06493276
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-10
[patent_title] => 'Word line boost circuit'
[patent_app_type] => B2
[patent_app_number] => 09/355653
[patent_app_country] => US
[patent_app_date] => 1999-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3382
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/493/06493276.pdf
[firstpage_image] =>[orig_patent_app_number] => 09355653
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/355653 | Word line boost circuit | Aug 1, 1999 | Issued |
Array
(
[id] => 4102860
[patent_doc_number] => 06134162
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Voltage generator with first drive current in test mode and second drive current in normal operation'
[patent_app_type] => 1
[patent_app_number] => 9/360952
[patent_app_country] => US
[patent_app_date] => 1999-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3104
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/134/06134162.pdf
[firstpage_image] =>[orig_patent_app_number] => 360952
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/360952 | Voltage generator with first drive current in test mode and second drive current in normal operation | Jul 26, 1999 | Issued |
Array
(
[id] => 4197159
[patent_doc_number] => 06094378
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'System for improved memory cell access'
[patent_app_type] => 1
[patent_app_number] => 9/348794
[patent_app_country] => US
[patent_app_date] => 1999-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2438
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/094/06094378.pdf
[firstpage_image] =>[orig_patent_app_number] => 348794
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/348794 | System for improved memory cell access | Jul 6, 1999 | Issued |
Array
(
[id] => 4417692
[patent_doc_number] => 06172932
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'On-chip voltage generating device for semiconductor memory with reduced stand-by current'
[patent_app_type] => 1
[patent_app_number] => 9/343560
[patent_app_country] => US
[patent_app_date] => 1999-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 3681
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/172/06172932.pdf
[firstpage_image] =>[orig_patent_app_number] => 343560
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/343560 | On-chip voltage generating device for semiconductor memory with reduced stand-by current | Jun 29, 1999 | Issued |
Array
(
[id] => 4229866
[patent_doc_number] => 06111795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Memory device having row decoder'
[patent_app_type] => 1
[patent_app_number] => 9/342059
[patent_app_country] => US
[patent_app_date] => 1999-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 8067
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/111/06111795.pdf
[firstpage_image] =>[orig_patent_app_number] => 342059
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/342059 | Memory device having row decoder | Jun 28, 1999 | Issued |
Array
(
[id] => 4171814
[patent_doc_number] => 06115316
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type'
[patent_app_type] => 1
[patent_app_number] => 9/342060
[patent_app_country] => US
[patent_app_date] => 1999-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 24
[patent_no_of_words] => 7850
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/115/06115316.pdf
[firstpage_image] =>[orig_patent_app_number] => 342060
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/342060 | Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type | Jun 28, 1999 | Issued |
| 09/342725 | SEMICONDUCTOR DEVICE AND A METHOD OF OPERATING THE SAME | Jun 28, 1999 | Abandoned |
Array
(
[id] => 4369308
[patent_doc_number] => 06169697
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Memory device with sensing current-reducible memory cell array'
[patent_app_type] => 1
[patent_app_number] => 9/340359
[patent_app_country] => US
[patent_app_date] => 1999-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5264
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/169/06169697.pdf
[firstpage_image] =>[orig_patent_app_number] => 340359
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/340359 | Memory device with sensing current-reducible memory cell array | Jun 27, 1999 | Issued |
Array
(
[id] => 4309041
[patent_doc_number] => 06181603
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Nonvolatile semiconductor memory device having plural memory cells which store multi-value information'
[patent_app_type] => 1
[patent_app_number] => 9/339960
[patent_app_country] => US
[patent_app_date] => 1999-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 38
[patent_no_of_words] => 17044
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/181/06181603.pdf
[firstpage_image] =>[orig_patent_app_number] => 339960
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/339960 | Nonvolatile semiconductor memory device having plural memory cells which store multi-value information | Jun 24, 1999 | Issued |
Array
(
[id] => 4396739
[patent_doc_number] => 06262923
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Semiconductor memory device with redundancy function'
[patent_app_type] => 1
[patent_app_number] => 9/339264
[patent_app_country] => US
[patent_app_date] => 1999-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 31
[patent_no_of_words] => 9659
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/262/06262923.pdf
[firstpage_image] =>[orig_patent_app_number] => 339264
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/339264 | Semiconductor memory device with redundancy function | Jun 22, 1999 | Issued |
Array
(
[id] => 4418658
[patent_doc_number] => 06310820
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'Relaxed write timing for a memory device'
[patent_app_type] => 1
[patent_app_number] => 9/335195
[patent_app_country] => US
[patent_app_date] => 1999-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6679
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/310/06310820.pdf
[firstpage_image] =>[orig_patent_app_number] => 335195
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/335195 | Relaxed write timing for a memory device | Jun 16, 1999 | Issued |
Array
(
[id] => 4316691
[patent_doc_number] => 06188594
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Reduced-pitch 6-transistor NMOS content-addressable-memory cell'
[patent_app_type] => 1
[patent_app_number] => 9/328957
[patent_app_country] => US
[patent_app_date] => 1999-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5280
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 380
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/188/06188594.pdf
[firstpage_image] =>[orig_patent_app_number] => 328957
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/328957 | Reduced-pitch 6-transistor NMOS content-addressable-memory cell | Jun 8, 1999 | Issued |
Array
(
[id] => 1523320
[patent_doc_number] => 06414868
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Memory expansion module including multiple memory banks and a bank control circuit'
[patent_app_type] => B1
[patent_app_number] => 09/327058
[patent_app_country] => US
[patent_app_date] => 1999-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3047
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 300
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/414/06414868.pdf
[firstpage_image] =>[orig_patent_app_number] => 09327058
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/327058 | Memory expansion module including multiple memory banks and a bank control circuit | Jun 6, 1999 | Issued |
Array
(
[id] => 4110161
[patent_doc_number] => 06097628
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Multi-level memory circuit with regulated writing voltage'
[patent_app_type] => 1
[patent_app_number] => 9/202656
[patent_app_country] => US
[patent_app_date] => 1999-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2830
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/097/06097628.pdf
[firstpage_image] =>[orig_patent_app_number] => 202656
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/202656 | Multi-level memory circuit with regulated writing voltage | Jun 6, 1999 | Issued |
Array
(
[id] => 4309025
[patent_doc_number] => 06181602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Device and method for reading nonvolatile memory cells'
[patent_app_type] => 1
[patent_app_number] => 9/322460
[patent_app_country] => US
[patent_app_date] => 1999-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2939
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/181/06181602.pdf
[firstpage_image] =>[orig_patent_app_number] => 322460
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/322460 | Device and method for reading nonvolatile memory cells | May 27, 1999 | Issued |
Array
(
[id] => 4096010
[patent_doc_number] => 06163497
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/321760
[patent_app_country] => US
[patent_app_date] => 1999-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4567
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/163/06163497.pdf
[firstpage_image] =>[orig_patent_app_number] => 321760
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/321760 | Semiconductor memory device | May 27, 1999 | Issued |
Array
(
[id] => 4369233
[patent_doc_number] => 06219270
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Integrated circuit having dynamic memory with boosted plateline'
[patent_app_type] => 1
[patent_app_number] => 9/316558
[patent_app_country] => US
[patent_app_date] => 1999-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2465
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/219/06219270.pdf
[firstpage_image] =>[orig_patent_app_number] => 316558
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/316558 | Integrated circuit having dynamic memory with boosted plateline | May 23, 1999 | Issued |
Array
(
[id] => 4316720
[patent_doc_number] => 06188596
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Layout for semiconductor memory including multi-level sensing'
[patent_app_type] => 1
[patent_app_number] => 9/315459
[patent_app_country] => US
[patent_app_date] => 1999-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7430
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/188/06188596.pdf
[firstpage_image] =>[orig_patent_app_number] => 315459
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/315459 | Layout for semiconductor memory including multi-level sensing | May 19, 1999 | Issued |