Hoa Van Le

Array ( [id] => 4170451 [patent_doc_number] => 06157584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Redundancy circuit and method for semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/315458 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6446 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157584.pdf [firstpage_image] =>[orig_patent_app_number] => 315458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7027344 [patent_doc_number] => 20010014044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE EXHIBITING IMPROVED HIGH SPEED AND STABLE WRITE OPERATIONS' [patent_app_type] => new [patent_app_number] => 09/314156 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3708 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014044.pdf [firstpage_image] =>[orig_patent_app_number] => 09314156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185806 [patent_doc_number] => 06141288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Semiconductor memory device allowing change of refresh mode and address switching method therewith' [patent_app_type] => 1 [patent_app_number] => 9/314028 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 39 [patent_no_of_words] => 13435 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141288.pdf [firstpage_image] =>[orig_patent_app_number] => 314028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6139728 [patent_doc_number] => 20020001245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE PERMITTING IMPROVED INTEGRATION DENSITY AND REDUCED ACCESSING TIME' [patent_app_type] => new [patent_app_number] => 09/311560 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001245.pdf [firstpage_image] =>[orig_patent_app_number] => 09311560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110625 [patent_doc_number] => 06067250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method and apparatus for localizing point defects causing leakage currents in a non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 9/311257 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2188 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067250.pdf [firstpage_image] =>[orig_patent_app_number] => 311257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6893562 [patent_doc_number] => 20010015928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'MEMORY DEVICE WITH FASTER RESET OPERATION' [patent_app_type] => new [patent_app_number] => 09/307758 [patent_app_country] => US [patent_app_date] => 1999-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8959 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015928.pdf [firstpage_image] =>[orig_patent_app_number] => 09307758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4316898 [patent_doc_number] => 06188609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Ramped or stepped gate channel erase for flash memory application' [patent_app_type] => 1 [patent_app_number] => 9/307259 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 7860 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188609.pdf [firstpage_image] =>[orig_patent_app_number] => 307259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4116880 [patent_doc_number] => 06101121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Multi-level memory circuit with regulated reading voltage' [patent_app_type] => 1 [patent_app_number] => 9/202657 [patent_app_country] => US [patent_app_date] => 1999-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2467 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101121.pdf [firstpage_image] =>[orig_patent_app_number] => 202657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202200 [patent_doc_number] => 06154394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Data input-output circuit and semiconductor data storage device provided therewith' [patent_app_type] => 1 [patent_app_number] => 9/299857 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154394.pdf [firstpage_image] =>[orig_patent_app_number] => 299857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4231023 [patent_doc_number] => RE037273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Synchronous semiconductor device with discontinued functions at power down' [patent_app_type] => 2 [patent_app_number] => 9/296101 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/037/RE037273.pdf [firstpage_image] =>[orig_patent_app_number] => 296101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4197504 [patent_doc_number] => 06151237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'DRAM having each memory cell storing plural bit data' [patent_app_type] => 1 [patent_app_number] => 9/292665 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5642 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151237.pdf [firstpage_image] =>[orig_patent_app_number] => 292665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368580 [patent_doc_number] => 06175533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Multi-port memory cell with preset' [patent_app_type] => 1 [patent_app_number] => 9/291158 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4997 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175533.pdf [firstpage_image] =>[orig_patent_app_number] => 291158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425630 [patent_doc_number] => 06195306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/289660 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9403 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195306.pdf [firstpage_image] =>[orig_patent_app_number] => 289660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139935 [patent_doc_number] => 06128209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Semiconductor memory device having dummy bit and word lines' [patent_app_type] => 1 [patent_app_number] => 9/288659 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3790 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128209.pdf [firstpage_image] =>[orig_patent_app_number] => 288659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4262887 [patent_doc_number] => 06222777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Output circuit for alternating multiple bit line per column memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/289460 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222777.pdf [firstpage_image] =>[orig_patent_app_number] => 289460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4131416 [patent_doc_number] => 06072739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Semiconductor memory device capable of attaining higher speed data reading and writing operations by making equalization operation suitable for single data line' [patent_app_type] => 1 [patent_app_number] => 9/286458 [patent_app_country] => US [patent_app_date] => 1999-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4598 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072739.pdf [firstpage_image] =>[orig_patent_app_number] => 286458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368358 [patent_doc_number] => 06175518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Remote register hierarchy accessible using a serial data line' [patent_app_type] => 1 [patent_app_number] => 9/281612 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 9435 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175518.pdf [firstpage_image] =>[orig_patent_app_number] => 281612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318292 [patent_doc_number] => 06252818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Apparatus and method for operating a dual port memory cell' [patent_app_type] => 1 [patent_app_number] => 9/277659 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3653 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252818.pdf [firstpage_image] =>[orig_patent_app_number] => 277659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110377 [patent_doc_number] => 06097642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Bus-line midpoint holding circuit for high speed memory read operation' [patent_app_type] => 1 [patent_app_number] => 9/273559 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4671 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097642.pdf [firstpage_image] =>[orig_patent_app_number] => 273559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1480087 [patent_doc_number] => 06344995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-05 [patent_title] => 'Circuit for controlling the potential difference between the substrate and the control gate on non-volatile memory and its control method' [patent_app_type] => B2 [patent_app_number] => 09/272160 [patent_app_country] => US [patent_app_date] => 1999-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2395 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344995.pdf [firstpage_image] =>[orig_patent_app_number] => 09272160 [rel_patent_id] =>[rel_patent_doc_number] =>)