Search

Hoa Van Le

Examiner (ID: 13440, Phone: (571)272-1332 , Office: P/1721 )

Most Active Art Unit
1752
Art Unit(s)
1105, 1113, 1507, 1506, 1721, 1724, 1737, 1752, 1795
Total Applications
3483
Issued Applications
2664
Pending Applications
54
Abandoned Applications
766

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4093474 [patent_doc_number] => 06055190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Device and method for suppressing bit line column leakage during erase verification of a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/268557 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055190.pdf [firstpage_image] =>[orig_patent_app_number] => 268557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268557
Device and method for suppressing bit line column leakage during erase verification of a memory cell Mar 14, 1999 Issued
Array ( [id] => 4327767 [patent_doc_number] => 06243320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Synchronous semiconductor memory device capable of selecting column at high speed' [patent_app_type] => 1 [patent_app_number] => 9/265856 [patent_app_country] => US [patent_app_date] => 1999-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 53 [patent_no_of_words] => 22487 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243320.pdf [firstpage_image] =>[orig_patent_app_number] => 265856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/265856
Synchronous semiconductor memory device capable of selecting column at high speed Mar 10, 1999 Issued
Array ( [id] => 4147933 [patent_doc_number] => 06122206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Semiconductor memory device having means for outputting redundancy replacement selection signal for each bank' [patent_app_type] => 1 [patent_app_number] => 9/262257 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 7463 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122206.pdf [firstpage_image] =>[orig_patent_app_number] => 262257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262257
Semiconductor memory device having means for outputting redundancy replacement selection signal for each bank Mar 3, 1999 Issued
Array ( [id] => 7027325 [patent_doc_number] => 20010014031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELECTRICALLY PROGRAMABLE MEMORY MATRIX ARRAY' [patent_app_type] => new [patent_app_number] => 09/125258 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12994 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014031.pdf [firstpage_image] =>[orig_patent_app_number] => 09125258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/125258
Non-volatile semiconductor memory device having electrically programable memory matrix array Feb 28, 1999 Issued
Array ( [id] => 4204717 [patent_doc_number] => 06044022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays' [patent_app_type] => 1 [patent_app_number] => 9/258059 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 10665 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044022.pdf [firstpage_image] =>[orig_patent_app_number] => 258059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/258059
Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays Feb 25, 1999 Issued
Array ( [id] => 4126771 [patent_doc_number] => 06046936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Semiconductor, memory card, and data processing system' [patent_app_type] => 1 [patent_app_number] => 9/250157 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 67 [patent_no_of_words] => 19235 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046936.pdf [firstpage_image] =>[orig_patent_app_number] => 250157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/250157
Semiconductor, memory card, and data processing system Feb 15, 1999 Issued
Array ( [id] => 3925175 [patent_doc_number] => 06002617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Fast power up reference voltage circuit and method' [patent_app_type] => 1 [patent_app_number] => 9/244917 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4281 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002617.pdf [firstpage_image] =>[orig_patent_app_number] => 244917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244917
Fast power up reference voltage circuit and method Feb 9, 1999 Issued
Array ( [id] => 4171269 [patent_doc_number] => 06115278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Memory system with switching for data isolation' [patent_app_type] => 1 [patent_app_number] => 9/247256 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 22 [patent_no_of_words] => 7008 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115278.pdf [firstpage_image] =>[orig_patent_app_number] => 247256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247256
Memory system with switching for data isolation Feb 8, 1999 Issued
Array ( [id] => 4110614 [patent_doc_number] => 06097659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Power-up circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/239858 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2890 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097659.pdf [firstpage_image] =>[orig_patent_app_number] => 239858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239858
Power-up circuit for semiconductor memory device Jan 28, 1999 Issued
Array ( [id] => 4261614 [patent_doc_number] => 06137718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method for operating a non-volatile memory cell arrangement' [patent_app_type] => 1 [patent_app_number] => 9/230612 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4118 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137718.pdf [firstpage_image] =>[orig_patent_app_number] => 230612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/230612
Method for operating a non-volatile memory cell arrangement Jan 27, 1999 Issued
Array ( [id] => 4131216 [patent_doc_number] => 06072725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of erasing floating gate capacitor used in voltage regulator' [patent_app_type] => 1 [patent_app_number] => 9/237257 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3450 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072725.pdf [firstpage_image] =>[orig_patent_app_number] => 237257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237257
Method of erasing floating gate capacitor used in voltage regulator Jan 25, 1999 Issued
Array ( [id] => 3925266 [patent_doc_number] => 06002623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Semiconductor memory with test circuit' [patent_app_type] => 1 [patent_app_number] => 9/235468 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5746 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002623.pdf [firstpage_image] =>[orig_patent_app_number] => 235468 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/235468
Semiconductor memory with test circuit Jan 21, 1999 Issued
Array ( [id] => 4110702 [patent_doc_number] => 06097664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan' [patent_app_type] => 1 [patent_app_number] => 9/235356 [patent_app_country] => US [patent_app_date] => 1999-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4241 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097664.pdf [firstpage_image] =>[orig_patent_app_number] => 235356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/235356
Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan Jan 20, 1999 Issued
Array ( [id] => 4126742 [patent_doc_number] => 06046934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method and device for multi-level programming of a memory cell' [patent_app_type] => 1 [patent_app_number] => 9/229460 [patent_app_country] => US [patent_app_date] => 1999-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 8 [patent_no_of_words] => 3874 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046934.pdf [firstpage_image] =>[orig_patent_app_number] => 229460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229460
Method and device for multi-level programming of a memory cell Jan 11, 1999 Issued
Array ( [id] => 4202262 [patent_doc_number] => 06130852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Memory integrated circuit device including a memory having a configuration suitable for mixture with logic' [patent_app_type] => 1 [patent_app_number] => 9/226158 [patent_app_country] => US [patent_app_date] => 1999-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 17286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130852.pdf [firstpage_image] =>[orig_patent_app_number] => 226158 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226158
Memory integrated circuit device including a memory having a configuration suitable for mixture with logic Jan 6, 1999 Issued
Array ( [id] => 4187759 [patent_doc_number] => 06084805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Synchronous memory with programmable read latency' [patent_app_type] => 1 [patent_app_number] => 9/225938 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6001 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084805.pdf [firstpage_image] =>[orig_patent_app_number] => 225938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225938
Synchronous memory with programmable read latency Jan 5, 1999 Issued
Array ( [id] => 4155255 [patent_doc_number] => 06031770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Synchronous memory with programmable read latency' [patent_app_type] => 1 [patent_app_number] => 9/225939 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031770.pdf [firstpage_image] =>[orig_patent_app_number] => 225939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225939
Synchronous memory with programmable read latency Jan 5, 1999 Issued
Array ( [id] => 4102564 [patent_doc_number] => 06134141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories' [patent_app_type] => 1 [patent_app_number] => 9/224656 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6574 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134141.pdf [firstpage_image] =>[orig_patent_app_number] => 224656 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224656
Dynamic write process for high bandwidth multi-bit-per-cell and analog/multi-level non-volatile memories Dec 30, 1998 Issued
Array ( [id] => 4110315 [patent_doc_number] => 06097639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'System and method for programming nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 9/221859 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 8912 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097639.pdf [firstpage_image] =>[orig_patent_app_number] => 221859 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221859
System and method for programming nonvolatile memory Dec 28, 1998 Issued
Array ( [id] => 1523362 [patent_doc_number] => 06414888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor storage device having burn-in mode' [patent_app_type] => B2 [patent_app_number] => 09/212310 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8946 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414888.pdf [firstpage_image] =>[orig_patent_app_number] => 09212310 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212310
Semiconductor storage device having burn-in mode Dec 15, 1998 Issued
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