Hoai V Ho

Array ( [id] => 18712553 [patent_doc_number] => 20230335186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => WRITE ASSIST CIRCUIT FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/720154 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18165230 [patent_doc_number] => 20230031828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => Memory device, memory test circuit and memory test method thereof having repair information maintaining mechanism [patent_app_type] => utility [patent_app_number] => 17/718356 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18839990 [patent_doc_number] => 11848069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Page buffer including latches and memory device including the page buffer [patent_app_type] => utility [patent_app_number] => 17/718070 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 10417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18696063 [patent_doc_number] => 20230326494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => NON-DESTRUCTIVE PATTERN IDENTIFICATION AT A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/716580 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18679504 [patent_doc_number] => 20230317160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MEMORY SYSTEM WITH PHYSICAL UNCLONABLE FUNCTION [patent_app_type] => utility [patent_app_number] => 17/710442 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18307907 [patent_doc_number] => 20230111807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => LATCH CIRCUIT, TRANSMISSION CIRCUIT INCLUDING LATCH CIRCUIT, AND SEMICONDUCTOR APPARATUS INCLUDING TRANSMISSION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/703646 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18998924 [patent_doc_number] => 11915778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Semiconductor memory device outputting data from memory cell groups in parallel and system [patent_app_type] => utility [patent_app_number] => 17/654890 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 21452 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18766738 [patent_doc_number] => 11817145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Programming multi-level memory cells [patent_app_type] => utility [patent_app_number] => 17/691684 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 20387 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17660441 [patent_doc_number] => 20220180906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => DATA SORTING CONTROL CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/678488 [patent_app_country] => US [patent_app_date] => 2022-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17833356 [patent_doc_number] => 20220270660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY DEVICE WITH LONG RETENTION AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/674301 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18607840 [patent_doc_number] => 11749316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Providing power availability information to memory [patent_app_type] => utility [patent_app_number] => 17/671000 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5980 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18721292 [patent_doc_number] => 11798644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Hierarchical ROM encoder system for performing address fault detection in a memory system [patent_app_type] => utility [patent_app_number] => 17/669793 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4664 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18735509 [patent_doc_number] => 11804250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Memory with deferred fractional row activation [patent_app_type] => utility [patent_app_number] => 17/665760 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 16510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18950766 [patent_doc_number] => 11894069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Unselected sub-block source line and bit line pre-charging to reduce read disturb [patent_app_type] => utility [patent_app_number] => 17/591361 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18950753 [patent_doc_number] => 11894055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/578840 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12717 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19313377 [patent_doc_number] => 12039191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => System and method for pre-soft-decoding tracking for NAND flash memories [patent_app_type] => utility [patent_app_number] => 17/574929 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 11747 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17566294 [patent_doc_number] => 20220130443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => 1S-1T FERROELECTRIC MEMORY [patent_app_type] => utility [patent_app_number] => 17/570249 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18967261 [patent_doc_number] => 11901039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Multiple differential write clock signals with different phases [patent_app_type] => utility [patent_app_number] => 17/556570 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8359 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17536461 [patent_doc_number] => 20220115070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => MEMORY SYSTEM FOR RESTRAINING THRESHOLD VARIATION TO IMPROVE DATA READING [patent_app_type] => utility [patent_app_number] => 17/556663 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18593122 [patent_doc_number] => 11742031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Memory system including the semiconductor memory and a controller [patent_app_type] => utility [patent_app_number] => 17/554710 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13328 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 416 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554710 [rel_patent_id] =>[rel_patent_doc_number] =>)