
Hoai V. Ho
Examiner (ID: 5108, Phone: (571)272-1777 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2312, 2818, 2511, 2827 |
| Total Applications | 2631 |
| Issued Applications | 2404 |
| Pending Applications | 100 |
| Abandoned Applications | 151 |
Applications
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|---|---|---|---|
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