Search

Hoai V. Ho

Examiner (ID: 5108, Phone: (571)272-1777 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2312, 2818, 2511, 2827
Total Applications
2631
Issued Applications
2404
Pending Applications
100
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19582366 [patent_doc_number] => 12148492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Semiconductor device and semiconductor system for detecting an error occurred in a parity [patent_app_type] => utility [patent_app_number] => 17/941773 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9040 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941773
Semiconductor device and semiconductor system for detecting an error occurred in a parity Sep 8, 2022 Issued
Array ( [id] => 18097030 [patent_doc_number] => 20220415371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => MEMORY SYSTEMS FOR HIGH SPEED SCHEDULING [patent_app_type] => utility [patent_app_number] => 17/902562 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902562 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902562
Memory systems for high speed scheduling Sep 1, 2022 Issued
Array ( [id] => 18224970 [patent_doc_number] => 20230063964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => ELECTRONIC DEVICE, OVER-ERASE DETECTION AND ELIMINATION METHODS FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/899167 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899167
Electronic device, over-erase detection and elimination methods for memory cells Aug 29, 2022 Issued
Array ( [id] => 18097034 [patent_doc_number] => 20220415375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/896956 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896956
Semiconductor device Aug 25, 2022 Issued
Array ( [id] => 18394560 [patent_doc_number] => 20230162781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/822241 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822241
Anti-row-hammer memory device Aug 24, 2022 Issued
Array ( [id] => 19007454 [patent_doc_number] => 20240071525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => PLANE LEVEL DEDICATED STARTING PROGRAM VOLTAGE TO REDUCE PROGRAM TIME FOR MULTI-PLANE CONCURRENT PROGRAM OPERATION [patent_app_type] => utility [patent_app_number] => 17/895625 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895625
Plane level dedicated starting program voltage to reduce program time for multi-plane concurrent program operation Aug 24, 2022 Issued
Array ( [id] => 19414516 [patent_doc_number] => 12080350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Balancing data in memory [patent_app_type] => utility [patent_app_number] => 17/890912 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10869 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890912
Balancing data in memory Aug 17, 2022 Issued
Array ( [id] => 18990831 [patent_doc_number] => 20240062800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY (DRAM) ROW HAMMERING MITIGATION [patent_app_type] => utility [patent_app_number] => 17/890022 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890022
Dynamic random access memory (DRAM) row hammering mitigation Aug 16, 2022 Issued
Array ( [id] => 18039725 [patent_doc_number] => 20220383942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY AND OPERATION METHOD OF THE MEMORY [patent_app_type] => utility [patent_app_number] => 17/887554 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887554
Memory and operation method of the memory Aug 14, 2022 Issued
Array ( [id] => 18061431 [patent_doc_number] => 20220392517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SEMICONDUCTOR DEVICE HAVING PDA FUNCTION [patent_app_type] => utility [patent_app_number] => 17/888083 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888083 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888083
Semiconductor device having PDA function Aug 14, 2022 Issued
Array ( [id] => 18585736 [patent_doc_number] => 20230268000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/888294 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888294
Memory array Aug 14, 2022 Issued
Array ( [id] => 18008205 [patent_doc_number] => 20220366972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SYSTEMS AND METHODS TO STORE MULTI-LEVEL DATA [patent_app_type] => utility [patent_app_number] => 17/876149 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876149
Systems and methods to store multi-level data Jul 27, 2022 Issued
Array ( [id] => 17992949 [patent_doc_number] => 20220358986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE [patent_app_type] => utility [patent_app_number] => 17/872771 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872771
Semiconductor device verifying signal supplied from outside Jul 24, 2022 Issued
Array ( [id] => 19016062 [patent_doc_number] => 11923002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Varying-polarity read operations for polarity-written memory cells [patent_app_type] => utility [patent_app_number] => 17/869649 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16601 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869649
Varying-polarity read operations for polarity-written memory cells Jul 19, 2022 Issued
Array ( [id] => 18514378 [patent_doc_number] => 20230230633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SENSE AMPLIFYING CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/864669 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864669 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/864669
Sense amplifying circuit and method, and semiconductor memory Jul 13, 2022 Issued
Array ( [id] => 18285838 [patent_doc_number] => 20230101310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => EARLY DETECTION OF COMPRESSION STATUS USING INLINE METADATA [patent_app_type] => utility [patent_app_number] => 17/865102 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865102
Early detection of compression status using inline metadata Jul 13, 2022 Issued
Array ( [id] => 19016101 [patent_doc_number] => 11923041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Signal generator for controlling timing of signal in memory device [patent_app_type] => utility [patent_app_number] => 17/857743 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857743
Signal generator for controlling timing of signal in memory device Jul 4, 2022 Issued
Array ( [id] => 18323071 [patent_doc_number] => 20230121199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => BIT LINE SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/857015 [patent_app_country] => US [patent_app_date] => 2022-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857015
Bit line sense amplifier and memory device including the same Jul 2, 2022 Issued
Array ( [id] => 18890851 [patent_doc_number] => 11869628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Apparatuses and methods to perform low latency access of a memory [patent_app_type] => utility [patent_app_number] => 17/810520 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810520
Apparatuses and methods to perform low latency access of a memory Jun 30, 2022 Issued
Array ( [id] => 19168243 [patent_doc_number] => 11984154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Local amplifier circuit, data readout method, and memory [patent_app_type] => utility [patent_app_number] => 17/854161 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5369 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854161
Local amplifier circuit, data readout method, and memory Jun 29, 2022 Issued
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