
Hoai V. Ho
Examiner (ID: 15701)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2312, 2511 |
| Total Applications | 2584 |
| Issued Applications | 2371 |
| Pending Applications | 99 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1504353
[patent_doc_number] => 06487124
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-26
[patent_title] => 'Nonvolatile semiconductor storage device capable of correctly reading selected memory cell and read method'
[patent_app_type] => B2
[patent_app_number] => 09/955016
[patent_app_country] => US
[patent_app_date] => 2001-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 7407
[patent_no_of_claims] => 5
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[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/487/06487124.pdf
[firstpage_image] =>[orig_patent_app_number] => 09955016
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/955016 | Nonvolatile semiconductor storage device capable of correctly reading selected memory cell and read method | Sep 18, 2001 | Issued |
Array
(
[id] => 6719651
[patent_doc_number] => 20030053339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-20
[patent_title] => 'Nonvolatile semiconductor memory device having divided bit lines'
[patent_app_type] => new
[patent_app_number] => 09/956212
[patent_app_country] => US
[patent_app_date] => 2001-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0053/20030053339.pdf
[firstpage_image] =>[orig_patent_app_number] => 09956212
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/956212 | Nonvolatile semiconductor memory device having divided bit lines | Sep 17, 2001 | Issued |
Array
(
[id] => 1359300
[patent_doc_number] => 06584032
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-24
[patent_title] => 'Dynamic random access memory having a low power consumption mode, and method of operating the same'
[patent_app_type] => B2
[patent_app_number] => 09/949847
[patent_app_country] => US
[patent_app_date] => 2001-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
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[pdf_file] => patents/06/584/06584032.pdf
[firstpage_image] =>[orig_patent_app_number] => 09949847
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/949847 | Dynamic random access memory having a low power consumption mode, and method of operating the same | Sep 11, 2001 | Issued |
Array
(
[id] => 1470044
[patent_doc_number] => 06459632
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Semiconductor memory device having redundancy function'
[patent_app_type] => B1
[patent_app_number] => 09/945814
[patent_app_country] => US
[patent_app_date] => 2001-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/459/06459632.pdf
[firstpage_image] =>[orig_patent_app_number] => 09945814
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/945814 | Semiconductor memory device having redundancy function | Sep 4, 2001 | Issued |
Array
(
[id] => 6489099
[patent_doc_number] => 20020024860
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-28
[patent_title] => 'Semiconductor memory device capable of high speed plural parallel test, method of data writing therefor and parallel tester'
[patent_app_type] => new
[patent_app_number] => 09/943011
[patent_app_country] => US
[patent_app_date] => 2001-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
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[pdf_file] => publications/A1/0024/20020024860.pdf
[firstpage_image] =>[orig_patent_app_number] => 09943011
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/943011 | Semiconductor integrated circuit device having internal synchronizing circuit responsive to test mode signal | Aug 30, 2001 | Issued |
Array
(
[id] => 1354364
[patent_doc_number] => 06587395
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-01
[patent_title] => 'System to set burst mode in a device'
[patent_app_type] => B2
[patent_app_number] => 09/943713
[patent_app_country] => US
[patent_app_date] => 2001-08-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/587/06587395.pdf
[firstpage_image] =>[orig_patent_app_number] => 09943713
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/943713 | System to set burst mode in a device | Aug 29, 2001 | Issued |
Array
(
[id] => 1482901
[patent_doc_number] => 06452839
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Method for erasing data from a single electron resistor memory'
[patent_app_type] => B1
[patent_app_number] => 09/943726
[patent_app_country] => US
[patent_app_date] => 2001-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/452/06452839.pdf
[firstpage_image] =>[orig_patent_app_number] => 09943726
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/943726 | Method for erasing data from a single electron resistor memory | Aug 28, 2001 | Issued |
Array
(
[id] => 1358584
[patent_doc_number] => 06580655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-17
[patent_title] => 'Pre-charge circuit and method for memory devices with shared sense amplifiers'
[patent_app_type] => B2
[patent_app_number] => 09/941911
[patent_app_country] => US
[patent_app_date] => 2001-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3897
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[pdf_file] => patents/06/580/06580655.pdf
[firstpage_image] =>[orig_patent_app_number] => 09941911
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/941911 | Pre-charge circuit and method for memory devices with shared sense amplifiers | Aug 28, 2001 | Issued |
Array
(
[id] => 6139776
[patent_doc_number] => 20020001254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-03
[patent_title] => 'Synchronous semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 09/934691
[patent_app_country] => US
[patent_app_date] => 2001-08-23
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09934691
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/934691 | Synchronous semiconductor memory device | Aug 22, 2001 | Issued |
Array
(
[id] => 1145462
[patent_doc_number] => 06781914
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[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'Flash memory having a flexible bank partition'
[patent_app_type] => B2
[patent_app_number] => 09/938410
[patent_app_country] => US
[patent_app_date] => 2001-08-23
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09938410
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/938410 | Flash memory having a flexible bank partition | Aug 22, 2001 | Issued |
Array
(
[id] => 1427948
[patent_doc_number] => 06519198
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-11
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 09/935010
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[firstpage_image] =>[orig_patent_app_number] => 09935010
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/935010 | Semiconductor memory device | Aug 20, 2001 | Issued |
Array
(
[id] => 1431658
[patent_doc_number] => 06504748
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[patent_issue_date] => 2003-01-07
[patent_title] => 'Ferroelectric random access memory device'
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[firstpage_image] =>[orig_patent_app_number] => 09931617
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/931617 | Ferroelectric random access memory device | Aug 15, 2001 | Issued |
Array
(
[id] => 6686363
[patent_doc_number] => 20030030086
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[patent_issue_date] => 2003-02-13
[patent_title] => 'DRAM circuitry with a longer refresh period'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/682214 | DRAM circuitry with a longer refresh period | Aug 6, 2001 | Abandoned |
Array
(
[id] => 1600130
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[patent_title] => 'Semiconductor integrated circuit device and electronic equipment'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/921912 | Semiconductor integrated circuit device and electronic equipment | Aug 5, 2001 | Issued |
Array
(
[id] => 1354095
[patent_doc_number] => 06587375
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[patent_title] => 'Row decoder for a nonvolatile memory device'
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Array
(
[id] => 1431681
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[patent_title] => 'Double boosting scheme for NAND to improve program inhibit characteristics'
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Array
(
[id] => 5950083
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Array
(
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[patent_title] => 'VOLTAGE BOOST CIRCUIT USING SUPPLY VOLTAGE DETECTION TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS IN READ MODE VOLTAGES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/915018 | Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage | Jul 24, 2001 | Issued |
Array
(
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Array
(
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[patent_title] => 'Precision programming of nonvolatile memory cells'
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[firstpage_image] =>[orig_patent_app_number] => 09909817
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/909817 | Precision programming of nonvolatile memory cells | Jul 19, 2001 | Issued |