Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6094365 [patent_doc_number] => 20020051396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Synchronous semiconductor memory device and refresh method thereof' [patent_app_type] => new [patent_app_number] => 09/907910 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20020051396.pdf [firstpage_image] =>[orig_patent_app_number] => 09907910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907910
Synchronous semiconductor memory device and refresh method thereof Jul 18, 2001 Issued
Array ( [id] => 1417154 [patent_doc_number] => 06538955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor integrated circuit for which high voltage countermeasure was taken' [patent_app_type] => B2 [patent_app_number] => 09/906116 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7844 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538955.pdf [firstpage_image] =>[orig_patent_app_number] => 09906116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/906116
Semiconductor integrated circuit for which high voltage countermeasure was taken Jul 16, 2001 Issued
Array ( [id] => 1425631 [patent_doc_number] => 06525956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Ferroelectric capacitor memory' [patent_app_type] => B2 [patent_app_number] => 09/905111 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5128 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525956.pdf [firstpage_image] =>[orig_patent_app_number] => 09905111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905111
Ferroelectric capacitor memory Jul 15, 2001 Issued
Array ( [id] => 5827180 [patent_doc_number] => 20020067639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Row decoder of a NOR-type flash memory device' [patent_app_type] => new [patent_app_number] => 09/905612 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4476 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20020067639.pdf [firstpage_image] =>[orig_patent_app_number] => 09905612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905612
Row decoder of a NOR-type flash memory device Jul 12, 2001 Issued
Array ( [id] => 1454381 [patent_doc_number] => 06456539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for sensing a memory signal from a selected memory cell of a memory device' [patent_app_type] => B1 [patent_app_number] => 09/903919 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2138 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456539.pdf [firstpage_image] =>[orig_patent_app_number] => 09903919 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903919
Method and apparatus for sensing a memory signal from a selected memory cell of a memory device Jul 11, 2001 Issued
Array ( [id] => 6734437 [patent_doc_number] => 20030012072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Method and system for banking register file memory arrays' [patent_app_type] => new [patent_app_number] => 09/902914 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20030012072.pdf [firstpage_image] =>[orig_patent_app_number] => 09902914 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902914
Memory array with common word line Jul 10, 2001 Issued
Array ( [id] => 1427108 [patent_doc_number] => 06522573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Solid-state magnetic memory using ferromagnetic tunnel junctions' [patent_app_type] => B2 [patent_app_number] => 09/893612 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 10227 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522573.pdf [firstpage_image] =>[orig_patent_app_number] => 09893612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893612
Solid-state magnetic memory using ferromagnetic tunnel junctions Jun 28, 2001 Issued
Array ( [id] => 1383802 [patent_doc_number] => 06567287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays' [patent_app_type] => B2 [patent_app_number] => 09/896814 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4557 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567287.pdf [firstpage_image] =>[orig_patent_app_number] => 09896814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896814
Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays Jun 28, 2001 Issued
Array ( [id] => 6933889 [patent_doc_number] => 20010055233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/888414 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11716 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20010055233.pdf [firstpage_image] =>[orig_patent_app_number] => 09888414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888414
Semiconductor memory device having redundancy circuit for saving faulty memory cells Jun 25, 2001 Issued
Array ( [id] => 1294097 [patent_doc_number] => 06633497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Resistive cross point array of short-tolerant memory cells' [patent_app_type] => B2 [patent_app_number] => 09/887314 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3530 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633497.pdf [firstpage_image] =>[orig_patent_app_number] => 09887314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887314
Resistive cross point array of short-tolerant memory cells Jun 21, 2001 Issued
Array ( [id] => 1550300 [patent_doc_number] => 06445628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Row redundancy in a content addressable memory' [patent_app_type] => B1 [patent_app_number] => 09/886235 [patent_app_country] => US [patent_app_date] => 2001-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 11618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445628.pdf [firstpage_image] =>[orig_patent_app_number] => 09886235 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886235
Row redundancy in a content addressable memory Jun 17, 2001 Issued
Array ( [id] => 5887283 [patent_doc_number] => 20020012280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Nonvolatile semiconductor storage device' [patent_app_type] => new [patent_app_number] => 09/880114 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11744 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20020012280.pdf [firstpage_image] =>[orig_patent_app_number] => 09880114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880114
Nonvolatile semiconductor storage device Jun 13, 2001 Issued
Array ( [id] => 1410386 [patent_doc_number] => 06545918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor memory device having boosted voltage stabilization circuit' [patent_app_type] => B2 [patent_app_number] => 09/878112 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5770 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545918.pdf [firstpage_image] =>[orig_patent_app_number] => 09878112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878112
Semiconductor memory device having boosted voltage stabilization circuit Jun 7, 2001 Issued
Array ( [id] => 1417167 [patent_doc_number] => 06538956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor memory device for providing address access time and data access time at a high speed' [patent_app_type] => B2 [patent_app_number] => 09/867811 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2614 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538956.pdf [firstpage_image] =>[orig_patent_app_number] => 09867811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867811
Semiconductor memory device for providing address access time and data access time at a high speed May 29, 2001 Issued
Array ( [id] => 1396444 [patent_doc_number] => 06560159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Block arrangement for semiconductor memory apparatus' [patent_app_type] => B2 [patent_app_number] => 09/867212 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 12119 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560159.pdf [firstpage_image] =>[orig_patent_app_number] => 09867212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867212
Block arrangement for semiconductor memory apparatus May 28, 2001 Issued
Array ( [id] => 6901168 [patent_doc_number] => 20010022751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Redundancy circuit of semiconductor memory' [patent_app_type] => new [patent_app_number] => 09/861843 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 19202 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022751.pdf [firstpage_image] =>[orig_patent_app_number] => 09861843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861843
Redundancy circuit of semiconductor memory May 21, 2001 Issued
Array ( [id] => 1431734 [patent_doc_number] => 06504779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Resistive cross point memory with on-chip sense amplifier calibration method and apparatus' [patent_app_type] => B2 [patent_app_number] => 09/855118 [patent_app_country] => US [patent_app_date] => 2001-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5729 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504779.pdf [firstpage_image] =>[orig_patent_app_number] => 09855118 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/855118
Resistive cross point memory with on-chip sense amplifier calibration method and apparatus May 13, 2001 Issued
Array ( [id] => 1550214 [patent_doc_number] => 06445606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Secure poly fuse ROM with a power-on or on-reset hardware security features and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/852018 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2591 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445606.pdf [firstpage_image] =>[orig_patent_app_number] => 09852018 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/852018
Secure poly fuse ROM with a power-on or on-reset hardware security features and method therefor May 9, 2001 Issued
Array ( [id] => 6901171 [patent_doc_number] => 20010022754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Synchronous memory with programmable read latency' [patent_app_type] => new [patent_app_number] => 09/847577 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5915 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022754.pdf [firstpage_image] =>[orig_patent_app_number] => 09847577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847577
Synchronous memory with programmable read latency Apr 30, 2001 Issued
Array ( [id] => 1507346 [patent_doc_number] => 06466478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/847115 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3661 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466478.pdf [firstpage_image] =>[orig_patent_app_number] => 09847115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847115
Non-volatile semiconductor memory device Apr 30, 2001 Issued
Menu