Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1454299 [patent_doc_number] => 06456521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Hierarchical bitline DRAM architecture system' [patent_app_type] => B1 [patent_app_number] => 09/814418 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5310 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456521.pdf [firstpage_image] =>[orig_patent_app_number] => 09814418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814418
Hierarchical bitline DRAM architecture system Mar 20, 2001 Issued
Array ( [id] => 1523390 [patent_doc_number] => 06414902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-02 [patent_title] => 'Use of setup time to send signal through die' [patent_app_type] => B2 [patent_app_number] => 09/813274 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4772 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414902.pdf [firstpage_image] =>[orig_patent_app_number] => 09813274 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813274
Use of setup time to send signal through die Mar 19, 2001 Issued
Array ( [id] => 7064200 [patent_doc_number] => 20010043486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Asymmetric ram cell' [patent_app_type] => new [patent_app_number] => 09/812659 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043486.pdf [firstpage_image] =>[orig_patent_app_number] => 09812659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812659
Asymmetric RAM cell Mar 18, 2001 Issued
Array ( [id] => 1523330 [patent_doc_number] => 06414873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'nvSRAM with multiple non-volatile memory cells for each SRAM memory cell' [patent_app_type] => B1 [patent_app_number] => 09/681317 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10278 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414873.pdf [firstpage_image] =>[orig_patent_app_number] => 09681317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681317
nvSRAM with multiple non-volatile memory cells for each SRAM memory cell Mar 15, 2001 Issued
Array ( [id] => 1425160 [patent_doc_number] => 06512694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-28 [patent_title] => 'NAND stack EEPROM with random programming capability' [patent_app_type] => B2 [patent_app_number] => 09/681314 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4276 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512694.pdf [firstpage_image] =>[orig_patent_app_number] => 09681314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681314
NAND stack EEPROM with random programming capability Mar 15, 2001 Issued
Array ( [id] => 1531148 [patent_doc_number] => 06480417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Global/local memory decode with independent program and read paths and shared local decode' [patent_app_type] => B2 [patent_app_number] => 09/809416 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3437 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480417.pdf [firstpage_image] =>[orig_patent_app_number] => 09809416 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809416
Global/local memory decode with independent program and read paths and shared local decode Mar 14, 2001 Issued
Array ( [id] => 6423006 [patent_doc_number] => 20020126539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Non-volatile memory device with erase address register' [patent_app_type] => new [patent_app_number] => 09/802612 [patent_app_country] => US [patent_app_date] => 2001-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4584 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126539.pdf [firstpage_image] =>[orig_patent_app_number] => 09802612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802612
Non-volatile memory device with erase address register Mar 8, 2001 Issued
Array ( [id] => 1426059 [patent_doc_number] => 06510071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Ferroelectric memory having memory cell array accessibility safeguards' [patent_app_type] => B2 [patent_app_number] => 09/800912 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5010 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510071.pdf [firstpage_image] =>[orig_patent_app_number] => 09800912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800912
Ferroelectric memory having memory cell array accessibility safeguards Mar 7, 2001 Issued
Array ( [id] => 1507384 [patent_doc_number] => 06466488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-15 [patent_title] => 'Reduction of data dependent power supply noise when sensing the state of a memory cell' [patent_app_type] => B2 [patent_app_number] => 09/802184 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466488.pdf [firstpage_image] =>[orig_patent_app_number] => 09802184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802184
Reduction of data dependent power supply noise when sensing the state of a memory cell Mar 7, 2001 Issued
Array ( [id] => 5857718 [patent_doc_number] => 20020122329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Low leakage current SRAM array' [patent_app_type] => new [patent_app_number] => 09/800015 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2113 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20020122329.pdf [firstpage_image] =>[orig_patent_app_number] => 09800015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/800015
Low leakage current SRAM array Mar 4, 2001 Issued
Array ( [id] => 1523342 [patent_doc_number] => 06414878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-02 [patent_title] => 'Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein' [patent_app_type] => B2 [patent_app_number] => 09/793749 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 80 [patent_no_of_words] => 31711 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 468 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414878.pdf [firstpage_image] =>[orig_patent_app_number] => 09793749 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/793749
Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein Feb 26, 2001 Issued
Array ( [id] => 6891630 [patent_doc_number] => 20010017792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other' [patent_app_type] => new [patent_app_number] => 09/790612 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5269 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017792.pdf [firstpage_image] =>[orig_patent_app_number] => 09790612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790612
SEMICONDUCTOR STORAGE DEVICE CONDUCTING A LATE-WRITE OPERATION AND CONTROLLING A TEST READ-OPERATION TO READ DATA NOT FROM A DATA LATCH CIRCUIT BUT FROM A MEMORY CORE CIRCUIT REGARDLESS OF WHETHER A PRECEDING ADDRESS AND A PRESENT ADDRESS MATCH EACH OTHER Feb 22, 2001 Issued
Array ( [id] => 6891651 [patent_doc_number] => 20010017813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/789514 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6266 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017813.pdf [firstpage_image] =>[orig_patent_app_number] => 09789514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789514
Semiconductor memory device Feb 21, 2001 Issued
Array ( [id] => 1600087 [patent_doc_number] => 06493264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Nonvolatile semiconductor memory, method of reading from and writing to the same and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/789816 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 52 [patent_no_of_words] => 9529 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493264.pdf [firstpage_image] =>[orig_patent_app_number] => 09789816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789816
Nonvolatile semiconductor memory, method of reading from and writing to the same and method of manufacturing the same Feb 21, 2001 Issued
Array ( [id] => 1531184 [patent_doc_number] => 06480427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Negative-potential detecting circuit having an enhanced sensitivity of detecting negative potentials' [patent_app_type] => B2 [patent_app_number] => 09/789712 [patent_app_country] => US [patent_app_date] => 2001-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 9601 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480427.pdf [firstpage_image] =>[orig_patent_app_number] => 09789712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789712
Negative-potential detecting circuit having an enhanced sensitivity of detecting negative potentials Feb 21, 2001 Issued
Array ( [id] => 1488664 [patent_doc_number] => 06366526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-02 [patent_title] => 'Static random access memory (SRAM) array central global decoder system and method' [patent_app_type] => B2 [patent_app_number] => 09/790132 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6585 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366526.pdf [firstpage_image] =>[orig_patent_app_number] => 09790132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790132
Static random access memory (SRAM) array central global decoder system and method Feb 20, 2001 Issued
Array ( [id] => 6272635 [patent_doc_number] => 20020105828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Double-bit non-voltatile memory unit and corresponding data read/write method' [patent_app_type] => new [patent_app_number] => 09/788017 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3659 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105828.pdf [firstpage_image] =>[orig_patent_app_number] => 09788017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788017
Double-bit non-voltatile memory unit and corresponding data read/write method Feb 14, 2001 Abandoned
Array ( [id] => 1212593 [patent_doc_number] => 06714476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Memory array with dual wordline operation' [patent_app_type] => B2 [patent_app_number] => 09/783918 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4285 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714476.pdf [firstpage_image] =>[orig_patent_app_number] => 09783918 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783918
Memory array with dual wordline operation Feb 14, 2001 Issued
Array ( [id] => 1555040 [patent_doc_number] => 06400593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Ternary CAM cell with DRAM mask circuit' [patent_app_type] => B1 [patent_app_number] => 09/780714 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 8863 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400593.pdf [firstpage_image] =>[orig_patent_app_number] => 09780714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780714
Ternary CAM cell with DRAM mask circuit Feb 7, 2001 Issued
Array ( [id] => 6062016 [patent_doc_number] => 20020031040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Semiconductor device including memory with reduced current consumption' [patent_app_type] => new [patent_app_number] => 09/775712 [patent_app_country] => US [patent_app_date] => 2001-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10813 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031040.pdf [firstpage_image] =>[orig_patent_app_number] => 09775712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775712
Semiconductor device including memory with reduced current consumption Feb 4, 2001 Issued
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