
Hoai V. Ho
Examiner (ID: 15701)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2312, 2511 |
| Total Applications | 2584 |
| Issued Applications | 2371 |
| Pending Applications | 99 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1454299
[patent_doc_number] => 06456521
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Hierarchical bitline DRAM architecture system'
[patent_app_type] => B1
[patent_app_number] => 09/814418
[patent_app_country] => US
[patent_app_date] => 2001-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5310
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/456/06456521.pdf
[firstpage_image] =>[orig_patent_app_number] => 09814418
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/814418 | Hierarchical bitline DRAM architecture system | Mar 20, 2001 | Issued |
Array
(
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[patent_doc_number] => 06414902
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-07-02
[patent_title] => 'Use of setup time to send signal through die'
[patent_app_type] => B2
[patent_app_number] => 09/813274
[patent_app_country] => US
[patent_app_date] => 2001-03-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/414/06414902.pdf
[firstpage_image] =>[orig_patent_app_number] => 09813274
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/813274 | Use of setup time to send signal through die | Mar 19, 2001 | Issued |
Array
(
[id] => 7064200
[patent_doc_number] => 20010043486
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-22
[patent_title] => 'Asymmetric ram cell'
[patent_app_type] => new
[patent_app_number] => 09/812659
[patent_app_country] => US
[patent_app_date] => 2001-03-19
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[pdf_file] => publications/A1/0043/20010043486.pdf
[firstpage_image] =>[orig_patent_app_number] => 09812659
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/812659 | Asymmetric RAM cell | Mar 18, 2001 | Issued |
Array
(
[id] => 1523330
[patent_doc_number] => 06414873
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'nvSRAM with multiple non-volatile memory cells for each SRAM memory cell'
[patent_app_type] => B1
[patent_app_number] => 09/681317
[patent_app_country] => US
[patent_app_date] => 2001-03-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/414/06414873.pdf
[firstpage_image] =>[orig_patent_app_number] => 09681317
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/681317 | nvSRAM with multiple non-volatile memory cells for each SRAM memory cell | Mar 15, 2001 | Issued |
Array
(
[id] => 1425160
[patent_doc_number] => 06512694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-28
[patent_title] => 'NAND stack EEPROM with random programming capability'
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[patent_app_number] => 09/681314
[patent_app_country] => US
[patent_app_date] => 2001-03-16
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[pdf_file] => patents/06/512/06512694.pdf
[firstpage_image] =>[orig_patent_app_number] => 09681314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/681314 | NAND stack EEPROM with random programming capability | Mar 15, 2001 | Issued |
Array
(
[id] => 1531148
[patent_doc_number] => 06480417
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-12
[patent_title] => 'Global/local memory decode with independent program and read paths and shared local decode'
[patent_app_type] => B2
[patent_app_number] => 09/809416
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[pdf_file] => patents/06/480/06480417.pdf
[firstpage_image] =>[orig_patent_app_number] => 09809416
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/809416 | Global/local memory decode with independent program and read paths and shared local decode | Mar 14, 2001 | Issued |
Array
(
[id] => 6423006
[patent_doc_number] => 20020126539
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-12
[patent_title] => 'Non-volatile memory device with erase address register'
[patent_app_type] => new
[patent_app_number] => 09/802612
[patent_app_country] => US
[patent_app_date] => 2001-03-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0126/20020126539.pdf
[firstpage_image] =>[orig_patent_app_number] => 09802612
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/802612 | Non-volatile memory device with erase address register | Mar 8, 2001 | Issued |
Array
(
[id] => 1426059
[patent_doc_number] => 06510071
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-21
[patent_title] => 'Ferroelectric memory having memory cell array accessibility safeguards'
[patent_app_type] => B2
[patent_app_number] => 09/800912
[patent_app_country] => US
[patent_app_date] => 2001-03-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/510/06510071.pdf
[firstpage_image] =>[orig_patent_app_number] => 09800912
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/800912 | Ferroelectric memory having memory cell array accessibility safeguards | Mar 7, 2001 | Issued |
Array
(
[id] => 1507384
[patent_doc_number] => 06466488
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-15
[patent_title] => 'Reduction of data dependent power supply noise when sensing the state of a memory cell'
[patent_app_type] => B2
[patent_app_number] => 09/802184
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[pdf_file] => patents/06/466/06466488.pdf
[firstpage_image] =>[orig_patent_app_number] => 09802184
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/802184 | Reduction of data dependent power supply noise when sensing the state of a memory cell | Mar 7, 2001 | Issued |
Array
(
[id] => 5857718
[patent_doc_number] => 20020122329
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-05
[patent_title] => 'Low leakage current SRAM array'
[patent_app_type] => new
[patent_app_number] => 09/800015
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09800015
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/800015 | Low leakage current SRAM array | Mar 4, 2001 | Issued |
Array
(
[id] => 1523342
[patent_doc_number] => 06414878
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[patent_kind] => B2
[patent_issue_date] => 2002-07-02
[patent_title] => 'Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein'
[patent_app_type] => B2
[patent_app_number] => 09/793749
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/793749 | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein | Feb 26, 2001 | Issued |
Array
(
[id] => 6891630
[patent_doc_number] => 20010017792
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[patent_kind] => A1
[patent_issue_date] => 2001-08-30
[patent_title] => 'Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless of whether a preceding address and a present address match each other'
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[firstpage_image] =>[orig_patent_app_number] => 09790612
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/790612 | SEMICONDUCTOR STORAGE DEVICE CONDUCTING A LATE-WRITE OPERATION AND CONTROLLING A TEST READ-OPERATION TO READ DATA NOT FROM A DATA LATCH CIRCUIT BUT FROM A MEMORY CORE CIRCUIT REGARDLESS OF WHETHER A PRECEDING ADDRESS AND A PRESENT ADDRESS MATCH EACH OTHER | Feb 22, 2001 | Issued |
Array
(
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Array
(
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[patent_title] => 'Nonvolatile semiconductor memory, method of reading from and writing to the same and method of manufacturing the same'
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Array
(
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[patent_title] => 'Negative-potential detecting circuit having an enhanced sensitivity of detecting negative potentials'
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Array
(
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[patent_title] => 'Static random access memory (SRAM) array central global decoder system and method'
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Array
(
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Array
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Array
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Array
(
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