Hoai V. Ho

Array ( [id] => 1603870 [patent_doc_number] => 06434053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Nonvolatile semiconductor memory device and method of operation thereof' [patent_app_type] => B1 [patent_app_number] => 09/729214 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 19706 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434053.pdf [firstpage_image] =>[orig_patent_app_number] => 09729214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6999310 [patent_doc_number] => 20010053091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Nonvolatile memory with background operation function' [patent_app_type] => new [patent_app_number] => 09/729415 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15355 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053091.pdf [firstpage_image] =>[orig_patent_app_number] => 09729415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6875600 [patent_doc_number] => 20010000693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'Synchronous semiconductor memory device capable of selecting column at high speed' [patent_app_type] => new-utility [patent_app_number] => 09/725851 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 23046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000693.pdf [firstpage_image] =>[orig_patent_app_number] => 09725851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1546784 [patent_doc_number] => 06373738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Low power CAM match line circuit' [patent_app_type] => B1 [patent_app_number] => 09/716511 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11311 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373738.pdf [firstpage_image] =>[orig_patent_app_number] => 09716511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7639181 [patent_doc_number] => 06396736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Nonvolatile semiconductor memory device which stores multi-value information' [patent_app_type] => B1 [patent_app_number] => 09/715106 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 17626 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396736.pdf [firstpage_image] =>[orig_patent_app_number] => 09715106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1442989 [patent_doc_number] => 06335879 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method of erasing and programming a flash memory in a single-chip microcomputer having a processing unit and memory' [patent_app_type] => B1 [patent_app_number] => 09/705835 [patent_app_country] => US [patent_app_date] => 2000-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 79 [patent_no_of_words] => 31914 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335879.pdf [firstpage_image] =>[orig_patent_app_number] => 09705835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507323 [patent_doc_number] => 06466470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Circuitry and method for resetting memory without a write cycle' [patent_app_type] => B1 [patent_app_number] => 09/706314 [patent_app_country] => US [patent_app_date] => 2000-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3528 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466470.pdf [firstpage_image] =>[orig_patent_app_number] => 09706314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1555174 [patent_doc_number] => 06400635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Memory circuitry for programmable logic integrated circuit devices' [patent_app_type] => B1 [patent_app_number] => 09/703914 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6138 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400635.pdf [firstpage_image] =>[orig_patent_app_number] => 09703914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1499223 [patent_doc_number] => 06404681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for erasing data from a non-volatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/703516 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 9222 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404681.pdf [firstpage_image] =>[orig_patent_app_number] => 09703516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1471586 [patent_doc_number] => 06407426 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Single electron resistor memory device and method' [patent_app_type] => B1 [patent_app_number] => 09/703364 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 8974 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407426.pdf [firstpage_image] =>[orig_patent_app_number] => 09703364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1428346 [patent_doc_number] => 06507527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Memory line discharge before sensing' [patent_app_type] => B1 [patent_app_number] => 09/698614 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1454 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507527.pdf [firstpage_image] =>[orig_patent_app_number] => 09698614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4329626 [patent_doc_number] => 06331952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Positive gate erasure for non-volatile memory cells' [patent_app_type] => 1 [patent_app_number] => 9/697810 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8944 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331952.pdf [firstpage_image] =>[orig_patent_app_number] => 697810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1427881 [patent_doc_number] => 06519191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Semiconductor integrated circuit device having an internal voltage generation circuit layout easily adaptable to change in specification' [patent_app_type] => B1 [patent_app_number] => 09/696011 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 59 [patent_no_of_words] => 25187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519191.pdf [firstpage_image] =>[orig_patent_app_number] => 09696011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1538601 [patent_doc_number] => 06490205 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Method of erasing a non-volatile memory cell using a substrate bias' [patent_app_type] => B1 [patent_app_number] => 09/697814 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 9119 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490205.pdf [firstpage_image] =>[orig_patent_app_number] => 09697814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1563062 [patent_doc_number] => 06362502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'DRAM cell circuit' [patent_app_type] => B1 [patent_app_number] => 09/692118 [patent_app_country] => US [patent_app_date] => 2000-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6255 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362502.pdf [firstpage_image] =>[orig_patent_app_number] => 09692118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1507397 [patent_doc_number] => 06466493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Memory configuration having redundant memory locations and method for accessing redundant memory locations' [patent_app_type] => B1 [patent_app_number] => 09/690298 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4232 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466493.pdf [firstpage_image] =>[orig_patent_app_number] => 09690298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1384265 [patent_doc_number] => 06567312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Non-volatile semiconductor memory device having a charge storing insulation film and data holding method therefor' [patent_app_type] => B1 [patent_app_number] => 09/689714 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567312.pdf [firstpage_image] =>[orig_patent_app_number] => 09689714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317851 [patent_doc_number] => 06327192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method and circuit for providing a memory device having hidden row access and row precharge times' [patent_app_type] => 1 [patent_app_number] => 9/685966 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9153 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327192.pdf [firstpage_image] =>[orig_patent_app_number] => 685966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1488568 [patent_doc_number] => 06366499 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method of operating flash memory' [patent_app_type] => B1 [patent_app_number] => 09/689026 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 33 [patent_no_of_words] => 7098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366499.pdf [firstpage_image] =>[orig_patent_app_number] => 09689026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4393476 [patent_doc_number] => 06304506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Energy-saving device for memory circuit' [patent_app_type] => 1 [patent_app_number] => 9/684116 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4263 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304506.pdf [firstpage_image] =>[orig_patent_app_number] => 684116 [rel_patent_id] =>[rel_patent_doc_number] =>)