Hoai V. Ho

Array ( [id] => 1565051 [patent_doc_number] => 06362990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Three port content addressable memory device and methods for implementing the same' [patent_app_type] => B1 [patent_app_number] => 09/654319 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4207 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362990.pdf [firstpage_image] =>[orig_patent_app_number] => 09654319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1603878 [patent_doc_number] => 06434061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Circuit configuration for enhancing performance characteristics of fabricated devices' [patent_app_type] => B1 [patent_app_number] => 09/654098 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3713 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434061.pdf [firstpage_image] =>[orig_patent_app_number] => 09654098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1480073 [patent_doc_number] => 06344990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'DRAM for storing data in pairs of cells' [patent_app_type] => B1 [patent_app_number] => 09/652015 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8676 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344990.pdf [firstpage_image] =>[orig_patent_app_number] => 09652015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1402170 [patent_doc_number] => 06552943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Sense amplifier for dynamic random access memory (DRAM) devices having enhanced read and write speed' [patent_app_type] => B1 [patent_app_number] => 09/652512 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2494 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552943.pdf [firstpage_image] =>[orig_patent_app_number] => 09652512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1488674 [patent_doc_number] => 06366529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Fast FiFo memory storage system' [patent_app_type] => B1 [patent_app_number] => 09/651214 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 8918 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366529.pdf [firstpage_image] =>[orig_patent_app_number] => 09651214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1061292 [patent_doc_number] => 06853582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Nonvolatile memory with controlled voltage boosting speed' [patent_app_type] => utility [patent_app_number] => 10/312014 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8059 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853582.pdf [firstpage_image] =>[orig_patent_app_number] => 10312014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1589937 [patent_doc_number] => 06359801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Low power memory module using restricted RAM activation' [patent_app_type] => B1 [patent_app_number] => 09/652226 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2927 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359801.pdf [firstpage_image] =>[orig_patent_app_number] => 09652226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318131 [patent_doc_number] => 06327208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Semiconductor memory device having self refresh mode' [patent_app_type] => 1 [patent_app_number] => 9/645610 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 5170 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327208.pdf [firstpage_image] =>[orig_patent_app_number] => 645610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1589991 [patent_doc_number] => 06359817 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Circuit and method for testing a memory device' [patent_app_type] => B1 [patent_app_number] => 09/640611 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3186 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359817.pdf [firstpage_image] =>[orig_patent_app_number] => 09640611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318021 [patent_doc_number] => 06327200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Circuit and method for testing a memory device' [patent_app_type] => 1 [patent_app_number] => 9/640610 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3105 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327200.pdf [firstpage_image] =>[orig_patent_app_number] => 640610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317743 [patent_doc_number] => 06327185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Semiconductor memory apparatus which can make read speed of memory cell faster' [patent_app_type] => 1 [patent_app_number] => 9/638310 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327185.pdf [firstpage_image] =>[orig_patent_app_number] => 638310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565159 [patent_doc_number] => 06363007 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Magneto-resistive memory with shared wordline and sense line' [patent_app_type] => B1 [patent_app_number] => 09/638415 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6299 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363007.pdf [firstpage_image] =>[orig_patent_app_number] => 09638415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478529 [patent_doc_number] => 06388939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Dual port sram' [patent_app_type] => B1 [patent_app_number] => 09/633514 [patent_app_country] => US [patent_app_date] => 2000-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388939.pdf [firstpage_image] =>[orig_patent_app_number] => 09633514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4273018 [patent_doc_number] => 06205077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'One-time programmable logic cell' [patent_app_type] => 1 [patent_app_number] => 9/575716 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1495 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205077.pdf [firstpage_image] =>[orig_patent_app_number] => 575716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419250 [patent_doc_number] => 06301166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Parallel tester capable of high speed plural parallel test' [patent_app_type] => 1 [patent_app_number] => 9/624601 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 47 [patent_no_of_words] => 15912 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301166.pdf [firstpage_image] =>[orig_patent_app_number] => 624601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317719 [patent_doc_number] => 06327184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Read circuit for a nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 9/621019 [patent_app_country] => US [patent_app_date] => 2000-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4956 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327184.pdf [firstpage_image] =>[orig_patent_app_number] => 621019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4279966 [patent_doc_number] => 06323664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Semiconductor memory device capable of accurately testing for defective memory cells at a wafer level' [patent_app_type] => 1 [patent_app_number] => 9/620018 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2770 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323664.pdf [firstpage_image] =>[orig_patent_app_number] => 620018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1437663 [patent_doc_number] => 06356476 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Sensing amplifier of nonvolatile ferroelectric memory device' [patent_app_type] => B1 [patent_app_number] => 09/620600 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9888 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356476.pdf [firstpage_image] =>[orig_patent_app_number] => 09620600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374013 [patent_doc_number] => 06256236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor device capable of implementing simultaneous signal input and output from and to the same external terminal' [patent_app_type] => 1 [patent_app_number] => 9/620716 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4031 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256236.pdf [firstpage_image] =>[orig_patent_app_number] => 620716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1463761 [patent_doc_number] => 06392939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Semiconductor memory device with improved defect elimination rate' [patent_app_type] => B1 [patent_app_number] => 09/615898 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6144 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392939.pdf [firstpage_image] =>[orig_patent_app_number] => 09615898 [rel_patent_id] =>[rel_patent_doc_number] =>)