Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4326400 [patent_doc_number] => 06317373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Semiconductor memory device having a test mode and semiconductor testing method utilizing the same' [patent_app_type] => 1 [patent_app_number] => 9/614610 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7913 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317373.pdf [firstpage_image] =>[orig_patent_app_number] => 614610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614610
Semiconductor memory device having a test mode and semiconductor testing method utilizing the same Jul 11, 2000 Issued
Array ( [id] => 4331569 [patent_doc_number] => 06249484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Synchronous memory with programmable read latency' [patent_app_type] => 1 [patent_app_number] => 9/613195 [patent_app_country] => US [patent_app_date] => 2000-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5821 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249484.pdf [firstpage_image] =>[orig_patent_app_number] => 613195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/613195
Synchronous memory with programmable read latency Jul 9, 2000 Issued
Array ( [id] => 4309462 [patent_doc_number] => 06198686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Memory device having row decoder' [patent_app_type] => 1 [patent_app_number] => 9/613583 [patent_app_country] => US [patent_app_date] => 2000-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8068 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198686.pdf [firstpage_image] =>[orig_patent_app_number] => 613583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/613583
Memory device having row decoder Jul 9, 2000 Issued
Array ( [id] => 4396837 [patent_doc_number] => 06262930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type' [patent_app_type] => 1 [patent_app_number] => 9/612281 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 7850 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262930.pdf [firstpage_image] =>[orig_patent_app_number] => 612281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/612281
Semiconductor memory device with overdriven sense amplifier and stabilized power-supply circuit of source follower type Jul 6, 2000 Issued
Array ( [id] => 1570354 [patent_doc_number] => 06377494 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Semiconductor device and electronic apparatus' [patent_app_type] => B1 [patent_app_number] => 09/610894 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377494.pdf [firstpage_image] =>[orig_patent_app_number] => 09610894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610894
Semiconductor device and electronic apparatus Jul 5, 2000 Issued
Array ( [id] => 1449993 [patent_doc_number] => 06370057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Semiconductor memory device having plate lines and precharge circuits' [patent_app_type] => B1 [patent_app_number] => 09/609774 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 9307 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370057.pdf [firstpage_image] =>[orig_patent_app_number] => 09609774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609774
Semiconductor memory device having plate lines and precharge circuits Jul 2, 2000 Issued
Array ( [id] => 4346250 [patent_doc_number] => 06333877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Static type semiconductor memory device that can suppress standby current' [patent_app_type] => 1 [patent_app_number] => 9/606316 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 40 [patent_no_of_words] => 16567 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333877.pdf [firstpage_image] =>[orig_patent_app_number] => 606316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606316
Static type semiconductor memory device that can suppress standby current Jun 28, 2000 Issued
Array ( [id] => 4283323 [patent_doc_number] => 06307793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Memory device, coupling noise eliminator, and coupling noise elimination method' [patent_app_type] => 1 [patent_app_number] => 9/604910 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4262 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307793.pdf [firstpage_image] =>[orig_patent_app_number] => 604910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604910
Memory device, coupling noise eliminator, and coupling noise elimination method Jun 27, 2000 Issued
Array ( [id] => 4407108 [patent_doc_number] => 06297992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'EPROM writing circuit' [patent_app_type] => 1 [patent_app_number] => 9/605714 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2919 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297992.pdf [firstpage_image] =>[orig_patent_app_number] => 605714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605714
EPROM writing circuit Jun 26, 2000 Issued
Array ( [id] => 4381160 [patent_doc_number] => 06275439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Power supply control apparatus for changing power line connection type in response to operation mode in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/604516 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2299 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275439.pdf [firstpage_image] =>[orig_patent_app_number] => 604516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604516
Power supply control apparatus for changing power line connection type in response to operation mode in semiconductor memory device Jun 26, 2000 Issued
Array ( [id] => 4384684 [patent_doc_number] => 06288971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Apparatus for generating data strobe signal applicable to double data rate SDRAM' [patent_app_type] => 1 [patent_app_number] => 9/603912 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2952 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288971.pdf [firstpage_image] =>[orig_patent_app_number] => 603912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603912
Apparatus for generating data strobe signal applicable to double data rate SDRAM Jun 25, 2000 Issued
Array ( [id] => 1488546 [patent_doc_number] => 06366492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Semiconductor memory device capable of automatically controlling bit-line recovery operation' [patent_app_type] => B1 [patent_app_number] => 09/595118 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6751 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366492.pdf [firstpage_image] =>[orig_patent_app_number] => 09595118 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595118
Semiconductor memory device capable of automatically controlling bit-line recovery operation Jun 15, 2000 Issued
Array ( [id] => 4298577 [patent_doc_number] => 06269034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor memory having a redundancy judgment circuit' [patent_app_type] => 1 [patent_app_number] => 9/593210 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4117 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269034.pdf [firstpage_image] =>[orig_patent_app_number] => 593210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593210
Semiconductor memory having a redundancy judgment circuit Jun 13, 2000 Issued
Array ( [id] => 4367737 [patent_doc_number] => 06201727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Nonvolatile ferroelectric random access memory device with segmented plate line scheme and a method for driving a plate line segment therein' [patent_app_type] => 1 [patent_app_number] => 9/591810 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3134 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201727.pdf [firstpage_image] =>[orig_patent_app_number] => 591810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/591810
Nonvolatile ferroelectric random access memory device with segmented plate line scheme and a method for driving a plate line segment therein Jun 11, 2000 Issued
Array ( [id] => 4420056 [patent_doc_number] => 06229742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Spare address decoder' [patent_app_type] => 1 [patent_app_number] => 9/590792 [patent_app_country] => US [patent_app_date] => 2000-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7654 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229742.pdf [firstpage_image] =>[orig_patent_app_number] => 590792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/590792
Spare address decoder Jun 7, 2000 Issued
Array ( [id] => 4331318 [patent_doc_number] => 06249467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Row redundancy in a content addressable memory' [patent_app_type] => 1 [patent_app_number] => 9/590779 [patent_app_country] => US [patent_app_date] => 2000-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 11497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249467.pdf [firstpage_image] =>[orig_patent_app_number] => 590779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/590779
Row redundancy in a content addressable memory Jun 7, 2000 Issued
Array ( [id] => 1546989 [patent_doc_number] => 06373783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor integrated circuit, method of controlling the same, and variable delay circuit' [patent_app_type] => B1 [patent_app_number] => 09/587296 [patent_app_country] => US [patent_app_date] => 2000-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 19028 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373783.pdf [firstpage_image] =>[orig_patent_app_number] => 09587296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/587296
Semiconductor integrated circuit, method of controlling the same, and variable delay circuit Jun 4, 2000 Issued
Array ( [id] => 4383934 [patent_doc_number] => 06288927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor memory device with column gate and equalizer circuitry' [patent_app_type] => 1 [patent_app_number] => 9/587263 [patent_app_country] => US [patent_app_date] => 2000-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 48 [patent_no_of_words] => 6638 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288927.pdf [firstpage_image] =>[orig_patent_app_number] => 587263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/587263
Semiconductor memory device with column gate and equalizer circuitry Jun 4, 2000 Issued
Array ( [id] => 1478563 [patent_doc_number] => 06388946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Circuit and method for incrementally selecting word lines' [patent_app_type] => B1 [patent_app_number] => 09/588114 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3263 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388946.pdf [firstpage_image] =>[orig_patent_app_number] => 09588114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588114
Circuit and method for incrementally selecting word lines May 30, 2000 Issued
Array ( [id] => 4384395 [patent_doc_number] => 06288952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'System for improved memory cell access' [patent_app_type] => 1 [patent_app_number] => 9/583040 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2438 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288952.pdf [firstpage_image] =>[orig_patent_app_number] => 583040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583040
System for improved memory cell access May 29, 2000 Issued
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