Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1538442 [patent_doc_number] => 06337816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Column redundancy circuit for semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/578865 [patent_app_country] => US [patent_app_date] => 2000-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4285 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337816.pdf [firstpage_image] =>[orig_patent_app_number] => 09578865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578865
Column redundancy circuit for semiconductor memory May 25, 2000 Issued
Array ( [id] => 4384027 [patent_doc_number] => 06288930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/578913 [patent_app_country] => US [patent_app_date] => 2000-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5825 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288930.pdf [firstpage_image] =>[orig_patent_app_number] => 578913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578913
Semiconductor memory device May 25, 2000 Issued
Array ( [id] => 1429346 [patent_doc_number] => 06515905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Nonvolatile semiconductor memory device having testing capabilities' [patent_app_type] => B2 [patent_app_number] => 09/578915 [patent_app_country] => US [patent_app_date] => 2000-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3580 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515905.pdf [firstpage_image] =>[orig_patent_app_number] => 09578915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578915
Nonvolatile semiconductor memory device having testing capabilities May 25, 2000 Issued
Array ( [id] => 7639185 [patent_doc_number] => 06396732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system' [patent_app_type] => B1 [patent_app_number] => 09/577149 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 11284 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396732.pdf [firstpage_image] =>[orig_patent_app_number] => 09577149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577149
Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system May 23, 2000 Issued
Array ( [id] => 4384278 [patent_doc_number] => 06288944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'NAND type nonvolatile memory with improved erase-verify operations' [patent_app_type] => 1 [patent_app_number] => 9/577373 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7663 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288944.pdf [firstpage_image] =>[orig_patent_app_number] => 577373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577373
NAND type nonvolatile memory with improved erase-verify operations May 22, 2000 Issued
Array ( [id] => 1433810 [patent_doc_number] => 06341100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Semiconductor integrated circuit having circuit for writing data to memory cell' [patent_app_type] => B1 [patent_app_number] => 09/575363 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12364 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341100.pdf [firstpage_image] =>[orig_patent_app_number] => 09575363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/575363
Semiconductor integrated circuit having circuit for writing data to memory cell May 21, 2000 Issued
Array ( [id] => 4420159 [patent_doc_number] => 06229753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Semiconductor memory device capable of accurate control of internally produced power supply potential' [patent_app_type] => 1 [patent_app_number] => 9/576229 [patent_app_country] => US [patent_app_date] => 2000-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11411 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229753.pdf [firstpage_image] =>[orig_patent_app_number] => 576229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576229
Semiconductor memory device capable of accurate control of internally produced power supply potential May 21, 2000 Issued
Array ( [id] => 1546971 [patent_doc_number] => 06373779 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Block RAM having multiple configurable write modes for use in a field programmable gate array' [patent_app_type] => B1 [patent_app_number] => 09/574300 [patent_app_country] => US [patent_app_date] => 2000-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7820 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373779.pdf [firstpage_image] =>[orig_patent_app_number] => 09574300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574300
Block RAM having multiple configurable write modes for use in a field programmable gate array May 18, 2000 Issued
Array ( [id] => 4341815 [patent_doc_number] => 06320787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Nonvolatile memory with illegitimate read preventing capability' [patent_app_type] => 1 [patent_app_number] => 9/572319 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4990 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320787.pdf [firstpage_image] =>[orig_patent_app_number] => 572319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572319
Nonvolatile memory with illegitimate read preventing capability May 17, 2000 Issued
Array ( [id] => 4419960 [patent_doc_number] => 06266271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Nonvolatile semiconductor memory for preventing unauthorized copying' [patent_app_type] => 1 [patent_app_number] => 9/572318 [patent_app_country] => US [patent_app_date] => 2000-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4638 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266271.pdf [firstpage_image] =>[orig_patent_app_number] => 572318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572318
Nonvolatile semiconductor memory for preventing unauthorized copying May 17, 2000 Issued
Array ( [id] => 4419898 [patent_doc_number] => 06266265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Memory module using a vacant pin terminal for balancing parasitic capacitive loads' [patent_app_type] => 1 [patent_app_number] => 9/572661 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2182 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266265.pdf [firstpage_image] =>[orig_patent_app_number] => 572661 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572661
Memory module using a vacant pin terminal for balancing parasitic capacitive loads May 15, 2000 Issued
Array ( [id] => 4318207 [patent_doc_number] => 06252812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Semiconductor memory device utilizing multiple edges of a signal' [patent_app_type] => 1 [patent_app_number] => 9/571916 [patent_app_country] => US [patent_app_date] => 2000-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5526 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252812.pdf [firstpage_image] =>[orig_patent_app_number] => 571916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571916
Semiconductor memory device utilizing multiple edges of a signal May 15, 2000 Issued
Array ( [id] => 4262595 [patent_doc_number] => 06222758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Semiconductor memory device having at least two layers of bit lines' [patent_app_type] => 1 [patent_app_number] => 9/571023 [patent_app_country] => US [patent_app_date] => 2000-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7373 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222758.pdf [firstpage_image] =>[orig_patent_app_number] => 571023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571023
Semiconductor memory device having at least two layers of bit lines May 14, 2000 Issued
Array ( [id] => 4374350 [patent_doc_number] => 06256260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Synchronous semiconductor memory device having input buffers and latch circuits' [patent_app_type] => 1 [patent_app_number] => 9/570729 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3995 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256260.pdf [firstpage_image] =>[orig_patent_app_number] => 570729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570729
Synchronous semiconductor memory device having input buffers and latch circuits May 11, 2000 Issued
Array ( [id] => 1565134 [patent_doc_number] => 06363001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'ROM with a reduced static consumption' [patent_app_type] => B1 [patent_app_number] => 09/569563 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1481 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363001.pdf [firstpage_image] =>[orig_patent_app_number] => 09569563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569563
ROM with a reduced static consumption May 11, 2000 Issued
Array ( [id] => 4345078 [patent_doc_number] => 06314049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Elimination of precharge operation in synchronous flash memory' [patent_app_type] => 1 [patent_app_number] => 9/568935 [patent_app_country] => US [patent_app_date] => 2000-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 13293 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314049.pdf [firstpage_image] =>[orig_patent_app_number] => 568935 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/568935
Elimination of precharge operation in synchronous flash memory May 10, 2000 Issued
Array ( [id] => 4317521 [patent_doc_number] => 06327172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Ferroelectric non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 9/567865 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 23 [patent_no_of_words] => 5067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327172.pdf [firstpage_image] =>[orig_patent_app_number] => 567865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567865
Ferroelectric non-volatile memory device May 8, 2000 Issued
Array ( [id] => 4286681 [patent_doc_number] => 06324095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Low voltage flash EEPROM memory cell with improved data retention' [patent_app_type] => 1 [patent_app_number] => 9/567521 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3506 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324095.pdf [firstpage_image] =>[orig_patent_app_number] => 567521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567521
Low voltage flash EEPROM memory cell with improved data retention May 8, 2000 Issued
Array ( [id] => 4363622 [patent_doc_number] => 06215704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor memory device allowing reduction in a number of external pins' [patent_app_type] => 1 [patent_app_number] => 9/564675 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 40 [patent_no_of_words] => 10614 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215704.pdf [firstpage_image] =>[orig_patent_app_number] => 564675 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564675
Semiconductor memory device allowing reduction in a number of external pins May 3, 2000 Issued
Array ( [id] => 7639176 [patent_doc_number] => 06396741 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Programming of nonvolatile memory cells' [patent_app_type] => B1 [patent_app_number] => 09/563923 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7513 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396741.pdf [firstpage_image] =>[orig_patent_app_number] => 09563923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/563923
Programming of nonvolatile memory cells May 3, 2000 Issued
Menu