
Hoai V Ho
Examiner (ID: 15701, Phone: (571)272-1777 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2312, 2511 |
| Total Applications | 2584 |
| Issued Applications | 2371 |
| Pending Applications | 99 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17173847
[patent_doc_number] => 20210327518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => NON-VOLATILE MEMORY WITH ERASE VERIFY SKIP
[patent_app_type] => utility
[patent_app_number] => 17/359208
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16596
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359208
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/359208 | Non-volatile memory with erase verify skip | Jun 24, 2021 | Issued |
Array
(
[id] => 18053879
[patent_doc_number] => 11527270
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-13
[patent_title] => Hybrid library latch array
[patent_app_type] => utility
[patent_app_number] => 17/359253
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 4348
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359253
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/359253 | Hybrid library latch array | Jun 24, 2021 | Issued |
Array
(
[id] => 17660451
[patent_doc_number] => 20220180916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => MEMORY DEVICE HAVING PLANES
[patent_app_type] => utility
[patent_app_number] => 17/349421
[patent_app_country] => US
[patent_app_date] => 2021-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10724
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349421
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/349421 | Memory device having planes | Jun 15, 2021 | Issued |
Array
(
[id] => 18174976
[patent_doc_number] => 11574693
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-07
[patent_title] => Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention
[patent_app_type] => utility
[patent_app_number] => 17/347772
[patent_app_country] => US
[patent_app_date] => 2021-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 23
[patent_no_of_words] => 14877
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347772
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/347772 | Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention | Jun 14, 2021 | Issued |
Array
(
[id] => 17130052
[patent_doc_number] => 20210304821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION
[patent_app_type] => utility
[patent_app_number] => 17/344146
[patent_app_country] => US
[patent_app_date] => 2021-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344146
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/344146 | Nonvolatile semiconductor memory device which performs improved erase operation | Jun 9, 2021 | Issued |
Array
(
[id] => 18137112
[patent_doc_number] => 11562800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-24
[patent_title] => Systems and methods for counting program-erase cycles of a cell block in a memory system
[patent_app_type] => utility
[patent_app_number] => 17/343486
[patent_app_country] => US
[patent_app_date] => 2021-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 10466
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343486
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/343486 | Systems and methods for counting program-erase cycles of a cell block in a memory system | Jun 8, 2021 | Issued |
Array
(
[id] => 18061414
[patent_doc_number] => 20220392500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-08
[patent_title] => PERFORMING READ OPERATIONS ON GROUPED MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 17/342171
[patent_app_country] => US
[patent_app_date] => 2021-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8383
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342171
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/342171 | Performing read operations on grouped memory cells | Jun 7, 2021 | Issued |
Array
(
[id] => 18219322
[patent_doc_number] => 11594268
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-28
[patent_title] => Memory device deserializer circuit with a reduced form factor
[patent_app_type] => utility
[patent_app_number] => 17/340754
[patent_app_country] => US
[patent_app_date] => 2021-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11272
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340754
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/340754 | Memory device deserializer circuit with a reduced form factor | Jun 6, 2021 | Issued |
Array
(
[id] => 17956154
[patent_doc_number] => 11482267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-25
[patent_title] => Memory device
[patent_app_type] => utility
[patent_app_number] => 17/330828
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 9308
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330828
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/330828 | Memory device | May 25, 2021 | Issued |
Array
(
[id] => 20110585
[patent_doc_number] => 12361309
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Method, device, storage medium and electronic device for data reading
[patent_app_type] => utility
[patent_app_number] => 18/039429
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 9983
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18039429
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/039429 | Method, device, storage medium and electronic device for data reading | May 25, 2021 | Issued |
Array
(
[id] => 17683210
[patent_doc_number] => 11367470
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-21
[patent_title] => Memory controller
[patent_app_type] => utility
[patent_app_number] => 17/321523
[patent_app_country] => US
[patent_app_date] => 2021-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5355
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321523
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/321523 | Memory controller | May 16, 2021 | Issued |
Array
(
[id] => 18120333
[patent_doc_number] => 11551731
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Memory circuit arrangement for accurate and secure read
[patent_app_type] => utility
[patent_app_number] => 17/321344
[patent_app_country] => US
[patent_app_date] => 2021-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 10404
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321344
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/321344 | Memory circuit arrangement for accurate and secure read | May 13, 2021 | Issued |
Array
(
[id] => 18379417
[patent_doc_number] => 20230154506
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => PRECHARGE CIRCUITRY FOR MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/998612
[patent_app_country] => US
[patent_app_date] => 2021-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9987
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998612
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/998612 | Precharge circuitry for memory | May 11, 2021 | Issued |
Array
(
[id] => 17716375
[patent_doc_number] => 11380373
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-07-05
[patent_title] => Memory with read circuit for current-to-voltage slope characteristic-based sensing and method
[patent_app_type] => utility
[patent_app_number] => 17/317938
[patent_app_country] => US
[patent_app_date] => 2021-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 13374
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317938
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/317938 | Memory with read circuit for current-to-voltage slope characteristic-based sensing and method | May 11, 2021 | Issued |
Array
(
[id] => 18120357
[patent_doc_number] => 11551755
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Semiconductor device including a content reference memory
[patent_app_type] => utility
[patent_app_number] => 17/318632
[patent_app_country] => US
[patent_app_date] => 2021-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8173
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318632
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/318632 | Semiconductor device including a content reference memory | May 11, 2021 | Issued |
Array
(
[id] => 18131152
[patent_doc_number] => 11557367
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Modifying memory bank operating parameters
[patent_app_type] => utility
[patent_app_number] => 17/317221
[patent_app_country] => US
[patent_app_date] => 2021-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 18620
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317221
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/317221 | Modifying memory bank operating parameters | May 10, 2021 | Issued |
Array
(
[id] => 18120341
[patent_doc_number] => 11551739
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Dual-precision analog memory cell and array
[patent_app_type] => utility
[patent_app_number] => 17/308675
[patent_app_country] => US
[patent_app_date] => 2021-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 5239
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17308675
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/308675 | Dual-precision analog memory cell and array | May 4, 2021 | Issued |
Array
(
[id] => 18131156
[patent_doc_number] => 11557371
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Imprint recovery for memory cells
[patent_app_type] => utility
[patent_app_number] => 17/241893
[patent_app_country] => US
[patent_app_date] => 2021-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 23
[patent_no_of_words] => 65640
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241893
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/241893 | Imprint recovery for memory cells | Apr 26, 2021 | Issued |
Array
(
[id] => 17359606
[patent_doc_number] => 20220020402
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-20
[patent_title] => SENSING CIRCUIT AND METHOD FOR MULTI-LEVEL MEMORY CELL
[patent_app_type] => utility
[patent_app_number] => 17/241112
[patent_app_country] => US
[patent_app_date] => 2021-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6449
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241112
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/241112 | Sensing circuit and method for multi-level memory cell | Apr 26, 2021 | Issued |
Array
(
[id] => 18047704
[patent_doc_number] => 11521662
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-06
[patent_title] => Write circuit of memory device
[patent_app_type] => utility
[patent_app_number] => 17/229676
[patent_app_country] => US
[patent_app_date] => 2021-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 10539
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229676
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/229676 | Write circuit of memory device | Apr 12, 2021 | Issued |