Search

Hoai V Ho

Examiner (ID: 15701, Phone: (571)272-1777 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17173809 [patent_doc_number] => 20210327480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING INPUT/OUTPUT PAD [patent_app_type] => utility [patent_app_number] => 17/076492 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076492
Semiconductor device including input/output pad Oct 20, 2020 Issued
Array ( [id] => 17522899 [patent_doc_number] => 20220108748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => TERNARY CONTENT ADDRESSABLE MEMORY AND MEMORY CELL THEREOF [patent_app_type] => utility [patent_app_number] => 17/065516 [patent_app_country] => US [patent_app_date] => 2020-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065516
Ternary content addressable memory and memory cell thereof Oct 6, 2020 Issued
Array ( [id] => 16730885 [patent_doc_number] => 20210098033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION [patent_app_type] => utility [patent_app_number] => 17/065278 [patent_app_country] => US [patent_app_date] => 2020-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065278 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065278
Deferred fractional memory row activation Oct 6, 2020 Issued
Array ( [id] => 16585803 [patent_doc_number] => 20210020205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY [patent_app_type] => utility [patent_app_number] => 17/062202 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062202
Providing power availability information to memory Oct 1, 2020 Issued
Array ( [id] => 17253831 [patent_doc_number] => 11189326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Non-destructive mode cache programming in NAND flash memory devices [patent_app_type] => utility [patent_app_number] => 17/062228 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062228 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062228
Non-destructive mode cache programming in NAND flash memory devices Oct 1, 2020 Issued
Array ( [id] => 16585831 [patent_doc_number] => 20210020233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => POLARIZATION GATE STACK SRAM [patent_app_type] => utility [patent_app_number] => 17/061272 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061272
Polarization gate stack SRAM Sep 30, 2020 Issued
Array ( [id] => 17508784 [patent_doc_number] => 20220101887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => MEMORY INTERCONNECTION ARCHITECTURE SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/037134 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037134 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037134
Memory interconnection architecture systems and methods Sep 28, 2020 Issued
Array ( [id] => 18067961 [patent_doc_number] => 20220399049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/775643 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17775643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/775643
Storage device with counter Sep 28, 2020 Issued
Array ( [id] => 17395709 [patent_doc_number] => 11244730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Memory system including the semiconductor memory and a controller [patent_app_type] => utility [patent_app_number] => 17/018511 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13318 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018511
Memory system including the semiconductor memory and a controller Sep 10, 2020 Issued
Array ( [id] => 16528500 [patent_doc_number] => 20200402581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => MEMORY SYSTEM FOR RESTRAINING THRESHOLD VARIATION TO IMPROVE DATA READING [patent_app_type] => utility [patent_app_number] => 17/014677 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014677 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014677
Memory system for restraining threshold variation to improve data reading Sep 7, 2020 Issued
Array ( [id] => 19213463 [patent_doc_number] => 12002535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Semiconductor device comprising memory cell array and arithmetic circuit [patent_app_type] => utility [patent_app_number] => 17/640452 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 33770 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17640452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/640452
Semiconductor device comprising memory cell array and arithmetic circuit Sep 7, 2020 Issued
Array ( [id] => 17188531 [patent_doc_number] => 20210335416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SEMICONDUCTOR DEVICES AND REFRESH METHODS USING THE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/011394 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011394 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011394
Semiconductor devices and refresh methods using the semiconductor devices Sep 2, 2020 Issued
Array ( [id] => 16515825 [patent_doc_number] => 20200395083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => SENSING CIRCUIT OF MEMORY DEVICE AND ASSOCIATED SENSING METHOD [patent_app_type] => utility [patent_app_number] => 17/008746 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008746
Sensing circuit of memory device and associated sensing method Aug 31, 2020 Issued
Array ( [id] => 17716378 [patent_doc_number] => 11380376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Apparatuses and methods to perform low latency access of a memory [patent_app_type] => utility [patent_app_number] => 17/003913 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6707 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003913
Apparatuses and methods to perform low latency access of a memory Aug 25, 2020 Issued
Array ( [id] => 17932969 [patent_doc_number] => 20220328095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MEMORY DEVICE, AND METHOD FOR DRIVING MEMORY [patent_app_type] => utility [patent_app_number] => 17/641500 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17641500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/641500
Memory device, and method for driving memory Aug 24, 2020 Issued
Array ( [id] => 18016128 [patent_doc_number] => 11508431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Logical operations using a logical operation component [patent_app_type] => utility [patent_app_number] => 17/001534 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001534 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001534
Logical operations using a logical operation component Aug 23, 2020 Issued
Array ( [id] => 17018154 [patent_doc_number] => 11087799 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Magnetic random access memory reference voltage generation [patent_app_type] => utility [patent_app_number] => 16/996675 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16996675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/996675
Magnetic random access memory reference voltage generation Aug 17, 2020 Issued
Array ( [id] => 17253861 [patent_doc_number] => 11189357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => Programmable memory device [patent_app_type] => utility [patent_app_number] => 16/989268 [patent_app_country] => US [patent_app_date] => 2020-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7096 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16989268 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/989268
Programmable memory device Aug 9, 2020 Issued
Array ( [id] => 16585812 [patent_doc_number] => 20210020214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/983604 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983604 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983604
Apparatuses and methods involving accessing distributed sub-blocks of memory cells Aug 2, 2020 Issued
Array ( [id] => 16425118 [patent_doc_number] => 20200350316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/933041 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933041
Semiconductor device including side surface conductor contact Jul 19, 2020 Issued
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