Search

Hoai V Ho

Examiner (ID: 15701, Phone: (571)272-1777 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17195863 [patent_doc_number] => 11164628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Compensating PCM drift for neuromorphic applications [patent_app_type] => utility [patent_app_number] => 16/797626 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797626
Compensating PCM drift for neuromorphic applications Feb 20, 2020 Issued
Array ( [id] => 17210484 [patent_doc_number] => 11170859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Memory device for passing verify operation and operating method of the same [patent_app_type] => utility [patent_app_number] => 16/796547 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 21769 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796547 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796547
Memory device for passing verify operation and operating method of the same Feb 19, 2020 Issued
Array ( [id] => 16911228 [patent_doc_number] => 11043276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-22 [patent_title] => Sense amplifier architecture providing improved memory performance [patent_app_type] => utility [patent_app_number] => 16/796270 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 16156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796270 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796270
Sense amplifier architecture providing improved memory performance Feb 19, 2020 Issued
Array ( [id] => 16937421 [patent_doc_number] => 20210203310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => LATCH CIRCUIT, MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/796800 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796800
Latch circuit, memory device and method Feb 19, 2020 Issued
Array ( [id] => 17152270 [patent_doc_number] => 11145357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Memory system, memory controller and method for operating memory system [patent_app_type] => utility [patent_app_number] => 16/796553 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796553 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796553
Memory system, memory controller and method for operating memory system Feb 19, 2020 Issued
Array ( [id] => 17486096 [patent_doc_number] => 20220093600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/427934 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17427934 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/427934
Semiconductor device and electronic device including the semiconductor device Feb 10, 2020 Issued
Array ( [id] => 16553132 [patent_doc_number] => 10886297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Semiconductor memory device including a laminated body with a plurality of semiconductor layers [patent_app_type] => utility [patent_app_number] => 16/785812 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 9552 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785812 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785812
Semiconductor memory device including a laminated body with a plurality of semiconductor layers Feb 9, 2020 Issued
Array ( [id] => 17002338 [patent_doc_number] => 11081160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Apparatus and methods for triggering row hammer address sampling [patent_app_type] => utility [patent_app_number] => 16/783063 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783063 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/783063
Apparatus and methods for triggering row hammer address sampling Feb 4, 2020 Issued
Array ( [id] => 16521436 [patent_doc_number] => 10872659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Memory system having write assist circuit including memory-adapted transistors [patent_app_type] => utility [patent_app_number] => 16/780739 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 17986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780739
Memory system having write assist circuit including memory-adapted transistors Feb 2, 2020 Issued
Array ( [id] => 17093118 [patent_doc_number] => 11121316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Symmetric tunable PCM resistor for artificial intelligence circuits [patent_app_type] => utility [patent_app_number] => 16/749042 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4493 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16749042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/749042
Symmetric tunable PCM resistor for artificial intelligence circuits Jan 21, 2020 Issued
Array ( [id] => 15938519 [patent_doc_number] => 20200160893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => APPARATUSES AND METHOD FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY FOR A VOLTAGE THRESHOLD COMPENSATION SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 16/747824 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747824
Apparatuses and method for reducing row address to column address delay for a voltage threshold compensation sense amplifier Jan 20, 2020 Issued
Array ( [id] => 16981207 [patent_doc_number] => 20210225444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => NON VOLATILE CROSS POINT MEMORY HAVING WORD LINE PASS TRANSISTOR WITH MULTIPLE ACTIVE STATES [patent_app_type] => utility [patent_app_number] => 16/748104 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748104
Non volatile cross point memory having word line pass transistor with multiple active states Jan 20, 2020 Issued
Array ( [id] => 16979572 [patent_doc_number] => 20210223809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => ON-CHIP PARAMETER GENERATION SYSTEM WITH AN INTEGRATED CALIBRATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/748674 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748674 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748674
On-chip parameter generation system with an integrated calibration circuit Jan 20, 2020 Issued
Array ( [id] => 16574796 [patent_doc_number] => 10896721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Controller architecture for reducing on-die capacitance [patent_app_type] => utility [patent_app_number] => 16/746365 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746365 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746365
Controller architecture for reducing on-die capacitance Jan 16, 2020 Issued
Array ( [id] => 15873741 [patent_doc_number] => 20200144274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => THREE-DIMENSIONAL MONOLITHIC VERTICAL TRANSISTOR MEMORY CELL WITH UNIFIED INTER-TIER CROSS-COUPLE [patent_app_type] => utility [patent_app_number] => 16/733772 [patent_app_country] => US [patent_app_date] => 2020-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733772 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/733772
Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple Jan 2, 2020 Issued
Array ( [id] => 16432668 [patent_doc_number] => 10832761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Polarization gate stack SRAM [patent_app_type] => utility [patent_app_number] => 16/732951 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732951 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732951
Polarization gate stack SRAM Jan 1, 2020 Issued
Array ( [id] => 15745259 [patent_doc_number] => 20200111519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE [patent_app_type] => utility [patent_app_number] => 16/709160 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/709160
Semiconductor device verifying signal supplied from outside Dec 9, 2019 Issued
Array ( [id] => 17152265 [patent_doc_number] => 11145352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Memory with adjustable TSV delay [patent_app_type] => utility [patent_app_number] => 16/706548 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7312 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706548 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706548
Memory with adjustable TSV delay Dec 5, 2019 Issued
Array ( [id] => 16180152 [patent_doc_number] => 20200227121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => STORAGE CELL USING CHARGE-TRAPPING DEVICES [patent_app_type] => utility [patent_app_number] => 16/703892 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703892 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703892
Storage cell using charge-trapping devices Dec 4, 2019 Issued
Array ( [id] => 16958874 [patent_doc_number] => 11062751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/704320 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9284 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704320
Memory device Dec 4, 2019 Issued
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