Search

Hoai V Ho

Examiner (ID: 15701, Phone: (571)272-1777 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16888690 [patent_doc_number] => 20210174887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => NON-VOLATILE MEMORY WITH ERASE VERIFY SKIP [patent_app_type] => utility [patent_app_number] => 16/704428 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704428
Non-volatile memory with erase verify skip Dec 4, 2019 Issued
Array ( [id] => 17416801 [patent_doc_number] => 20220051705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY AT HIGH SIGNALING RATES [patent_app_type] => utility [patent_app_number] => 17/299554 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17299554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/299554
DRAM interface mode with improved channel integrity and efficiency at high signaling rates Dec 1, 2019 Issued
Array ( [id] => 16372187 [patent_doc_number] => 10803953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Memory system for restraining threshold variation to improve data reading [patent_app_type] => utility [patent_app_number] => 16/697540 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11392 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697540 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697540
Memory system for restraining threshold variation to improve data reading Nov 26, 2019 Issued
Array ( [id] => 16973412 [patent_doc_number] => 11069391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Dual-precision analog memory cell and array [patent_app_type] => utility [patent_app_number] => 16/693332 [patent_app_country] => US [patent_app_date] => 2019-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5217 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693332
Dual-precision analog memory cell and array Nov 23, 2019 Issued
Array ( [id] => 17353007 [patent_doc_number] => 11227651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Static random access memory read path with latch [patent_app_type] => utility [patent_app_number] => 16/692714 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9909 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692714
Static random access memory read path with latch Nov 21, 2019 Issued
Array ( [id] => 16944387 [patent_doc_number] => 11056640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Magnetoresistive memory device including a high dielectric constant capping layer and methods of making the same [patent_app_type] => utility [patent_app_number] => 16/693006 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693006
Magnetoresistive memory device including a high dielectric constant capping layer and methods of making the same Nov 21, 2019 Issued
Array ( [id] => 16447977 [patent_doc_number] => 10839908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Semiconductor memory device applying different voltages to respective select gate lines [patent_app_type] => utility [patent_app_number] => 16/692374 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7118 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692374 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692374
Semiconductor memory device applying different voltages to respective select gate lines Nov 21, 2019 Issued
Array ( [id] => 17137480 [patent_doc_number] => 11139045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Memory device with a memory repair mechanism and methods for operating the same [patent_app_type] => utility [patent_app_number] => 16/693126 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 11603 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693126
Memory device with a memory repair mechanism and methods for operating the same Nov 21, 2019 Issued
Array ( [id] => 16479330 [patent_doc_number] => 10854283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory device with enhanced access capability and associated method [patent_app_type] => utility [patent_app_number] => 16/689852 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689852
Memory device with enhanced access capability and associated method Nov 19, 2019 Issued
Array ( [id] => 16911215 [patent_doc_number] => 11043263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-22 [patent_title] => Low offset and enhanced write margin for stacked fabric dies [patent_app_type] => utility [patent_app_number] => 16/683846 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4043 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683846
Low offset and enhanced write margin for stacked fabric dies Nov 13, 2019 Issued
Array ( [id] => 16880911 [patent_doc_number] => 11031067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Semiconductor memory device for securing sensing margin at cryogenic temperature [patent_app_type] => utility [patent_app_number] => 16/683926 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4521 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683926
Semiconductor memory device for securing sensing margin at cryogenic temperature Nov 13, 2019 Issued
Array ( [id] => 16637782 [patent_doc_number] => 10916296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/684564 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684564
Semiconductor structure and manufacturing method thereof Nov 13, 2019 Issued
Array ( [id] => 16738724 [patent_doc_number] => 10964385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-30 [patent_title] => Restoring memory cell threshold voltages [patent_app_type] => utility [patent_app_number] => 16/684526 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16959 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684526
Restoring memory cell threshold voltages Nov 13, 2019 Issued
Array ( [id] => 16827546 [patent_doc_number] => 20210142839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => Devices and Methods to Store an Initialization State [patent_app_type] => utility [patent_app_number] => 16/683192 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683192
Devices and methods to store an initialization state Nov 12, 2019 Issued
Array ( [id] => 15563875 [patent_doc_number] => 20200066349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/671692 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671692
Semiconductor memory system including a plurality of semiconductor memory devices Oct 31, 2019 Issued
Array ( [id] => 16818566 [patent_doc_number] => 11003392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Memory controller and method of operating the memory controller [patent_app_type] => utility [patent_app_number] => 16/672087 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 18335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672087 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/672087
Memory controller and method of operating the memory controller Oct 31, 2019 Issued
Array ( [id] => 15625651 [patent_doc_number] => 20200083230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => Integrated Assemblies Having Continuous High-Dielectric Films Extending Across Channel Regions of Adjacent Transistors [patent_app_type] => utility [patent_app_number] => 16/654172 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654172 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654172
Integrated assemblies having continuous high-dielectric films extending across channel regions of adjacent transistors Oct 15, 2019 Issued
Array ( [id] => 16372165 [patent_doc_number] => 10803931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Non-volatile memory having memory array with differential cells [patent_app_type] => utility [patent_app_number] => 16/581838 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9136 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 563 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581838 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/581838
Non-volatile memory having memory array with differential cells Sep 24, 2019 Issued
Array ( [id] => 16819654 [patent_doc_number] => 11004491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Twisted wordline structures [patent_app_type] => utility [patent_app_number] => 16/582474 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582474
Twisted wordline structures Sep 24, 2019 Issued
Array ( [id] => 15717111 [patent_doc_number] => 20200105323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => DATA RECEIVING CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/582322 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582322
Data receiving circuit Sep 24, 2019 Issued
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