Search

Hoai V Ho

Examiner (ID: 15701, Phone: (571)272-1777 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16723534 [patent_doc_number] => 20210090681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => IMPRINT RECOVERY FOR MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/580972 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 65594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580972 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/580972
Imprint recovery for memory cells Sep 23, 2019 Issued
Array ( [id] => 16723491 [patent_doc_number] => 20210090638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => PAGE BUFFER STRUCTURE AND FAST CONTINUOUS READ [patent_app_type] => utility [patent_app_number] => 16/581562 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581562 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/581562
Page buffer structure and fast continuous read Sep 23, 2019 Issued
Array ( [id] => 16803131 [patent_doc_number] => 10998082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Memory system for activating redundancy memory cell and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/568111 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568111
Memory system for activating redundancy memory cell and operating method thereof Sep 10, 2019 Issued
Array ( [id] => 16186882 [patent_doc_number] => 10720218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Nonvolatile memory device and an erase method thereof [patent_app_type] => utility [patent_app_number] => 16/563034 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12683 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563034 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563034
Nonvolatile memory device and an erase method thereof Sep 5, 2019 Issued
Array ( [id] => 16372193 [patent_doc_number] => 10803959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Memory system including the semiconductor memory and a controller [patent_app_type] => utility [patent_app_number] => 16/563045 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13309 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 472 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563045
Memory system including the semiconductor memory and a controller Sep 5, 2019 Issued
Array ( [id] => 16653397 [patent_doc_number] => 10930590 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Interconnect device and method [patent_app_type] => utility [patent_app_number] => 16/549110 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9352 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549110 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549110
Interconnect device and method Aug 22, 2019 Issued
Array ( [id] => 16707463 [patent_doc_number] => 10957405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Memory system configured to update write voltage applied to memory cells based on number of write or erase operations [patent_app_type] => utility [patent_app_number] => 16/548136 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548136 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548136
Memory system configured to update write voltage applied to memory cells based on number of write or erase operations Aug 21, 2019 Issued
Array ( [id] => 16431603 [patent_doc_number] => 10831685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Semiconductor memory systems with on-die data buffering [patent_app_type] => utility [patent_app_number] => 16/546694 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 35 [patent_no_of_words] => 13107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546694
Semiconductor memory systems with on-die data buffering Aug 20, 2019 Issued
Array ( [id] => 16300840 [patent_doc_number] => 20200286563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/546112 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546112 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546112
Semiconductor memory device in which a conductive line connected to a word line selected for programming is charged to a voltage larger than the program voltage Aug 19, 2019 Issued
Array ( [id] => 16575313 [patent_doc_number] => 10897244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-19 [patent_title] => Apparatuses and methods for voltage dependent delay [patent_app_type] => utility [patent_app_number] => 16/545384 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545384
Apparatuses and methods for voltage dependent delay Aug 19, 2019 Issued
Array ( [id] => 16660384 [patent_doc_number] => 20210057021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => APPARATUSES AND METHODS FOR ANALOG ROW ACCESS TRACKING [patent_app_type] => utility [patent_app_number] => 16/546152 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546152
Apparatuses and methods for analog row access tracking Aug 19, 2019 Issued
Array ( [id] => 16645318 [patent_doc_number] => 10923182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Fixed-level charge sharing type LCV for memory compiler [patent_app_type] => utility [patent_app_number] => 16/545834 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545834 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545834
Fixed-level charge sharing type LCV for memory compiler Aug 19, 2019 Issued
Array ( [id] => 17144953 [patent_doc_number] => 20210312966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => SEMICONDUCTOR CIRCUIT AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/250649 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250649 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250649
Semiconductor circuit and electronic device for storing information Aug 7, 2019 Issued
Array ( [id] => 15563805 [patent_doc_number] => 20200066314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION [patent_app_type] => utility [patent_app_number] => 16/528523 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528523 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528523
Deferred fractional memory row activation Jul 30, 2019 Issued
Array ( [id] => 16386245 [patent_doc_number] => 10811086 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => SRAM write yield enhancement with pull-up strength modulation [patent_app_type] => utility [patent_app_number] => 16/523350 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523350
SRAM write yield enhancement with pull-up strength modulation Jul 25, 2019 Issued
Array ( [id] => 16601283 [patent_doc_number] => 20210027814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => DATA PROCESSING SYSTEM AND METHOD FOR GENERATING A DIGITAL CODE WITH A PHYSICALLY UNCLONABLE FUNCTION [patent_app_type] => utility [patent_app_number] => 16/523284 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523284
Data processing system and method for generating a digital code with a physically unclonable function Jul 25, 2019 Issued
Array ( [id] => 16638181 [patent_doc_number] => 10916698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Semiconductor storage device including hexagonal insulating layer [patent_app_type] => utility [patent_app_number] => 16/523394 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4494 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523394 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523394
Semiconductor storage device including hexagonal insulating layer Jul 25, 2019 Issued
Array ( [id] => 16187587 [patent_doc_number] => 10720932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-21 [patent_title] => Digital to analog convertor, failure bit number detector and non-volatile semiconductor storage device [patent_app_type] => utility [patent_app_number] => 16/522684 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4284 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522684 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522684
Digital to analog convertor, failure bit number detector and non-volatile semiconductor storage device Jul 25, 2019 Issued
Array ( [id] => 15717127 [patent_doc_number] => 20200105331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => PURGEABLE MEMORY MAPPED FILES [patent_app_type] => utility [patent_app_number] => 16/522578 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522578 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522578
Purgeable memory mapped files Jul 24, 2019 Issued
Array ( [id] => 16536311 [patent_doc_number] => 10878924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Data storage device intergrating host read commands and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/517171 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6895 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517171
Data storage device intergrating host read commands and method of operating the same Jul 18, 2019 Issued
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