Search

Hoai V Ho

Examiner (ID: 15701, Phone: (571)272-1777 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16193888 [patent_doc_number] => 20200234737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => LEAKAGE CURRENT REDUCTION IN A DUAL RAIL DEVICE [patent_app_type] => utility [patent_app_number] => 16/253210 [patent_app_country] => US [patent_app_date] => 2019-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/253210
Leakage current reduction in a dual rail device Jan 20, 2019 Issued
Array ( [id] => 15351155 [patent_doc_number] => 20200013469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => COLUMN ERASING IN NON-VOLATILE MEMORY STRINGS [patent_app_type] => utility [patent_app_number] => 16/252300 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252300 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252300
Column erasing in non-volatile memory strings Jan 17, 2019 Issued
Array ( [id] => 16194241 [patent_doc_number] => 20200235090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BOND PAD-BASED POWER SUPPLY NETWORK FOR A SOURCE LINE AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/251954 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/251954
Three-dimensional memory device containing bond pad-based power supply network for a source line and methods of making the same Jan 17, 2019 Issued
Array ( [id] => 16067191 [patent_doc_number] => 10692555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Semiconductor memory devices enabling read strobe mode and related methods of operating semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 16/249594 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 11408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249594
Semiconductor memory devices enabling read strobe mode and related methods of operating semiconductor memory devices Jan 15, 2019 Issued
Array ( [id] => 14842589 [patent_doc_number] => 20190279695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/237346 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237346
Apparatuses and methods involving accessing distributed sub-blocks of memory cells Dec 30, 2018 Issued
Array ( [id] => 14541695 [patent_doc_number] => 20190206469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => DYNAMIC REFERENCE SCHEME FOR IMPROVING READ MARGIN OF RESISTIVE MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/234876 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234876 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234876
Dynamic reference scheme for improving read margin of resistive memory array Dec 27, 2018 Issued
Array ( [id] => 15759817 [patent_doc_number] => 10622035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-14 [patent_title] => Sense amplifier, sensing method and non-volatile memory using the same [patent_app_type] => utility [patent_app_number] => 16/234580 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234580 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234580
Sense amplifier, sensing method and non-volatile memory using the same Dec 27, 2018 Issued
Array ( [id] => 16147661 [patent_doc_number] => 10706905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Single path memory sense amplifier circuit [patent_app_type] => utility [patent_app_number] => 16/234954 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234954
Single path memory sense amplifier circuit Dec 27, 2018 Issued
Array ( [id] => 16119163 [patent_doc_number] => 20200211604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SENSE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/232916 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232916
Sensing architecture Dec 25, 2018 Issued
Array ( [id] => 16645316 [patent_doc_number] => 10923180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Sensing techniques using a charge transfer device [patent_app_type] => utility [patent_app_number] => 16/232280 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 25653 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232280 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232280
Sensing techniques using a charge transfer device Dec 25, 2018 Issued
Array ( [id] => 16080197 [patent_doc_number] => 20200194085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => SENSING CIRCUIT OF MEMORY DEVICE AND ASSOCIATED SENSING METHOD [patent_app_type] => utility [patent_app_number] => 16/222196 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222196
Sensing circuit of memory device and associated sensing method Dec 16, 2018 Issued
Array ( [id] => 16047623 [patent_doc_number] => 10685690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Memory device in which locations of registers storing fail addresses are merged [patent_app_type] => utility [patent_app_number] => 16/222114 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12807 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222114 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222114
Memory device in which locations of registers storing fail addresses are merged Dec 16, 2018 Issued
Array ( [id] => 15374281 [patent_doc_number] => 10528862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Neural network system and method for controlling the same [patent_app_type] => utility [patent_app_number] => 16/222222 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5874 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222222 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222222
Neural network system and method for controlling the same Dec 16, 2018 Issued
Array ( [id] => 14137515 [patent_doc_number] => 20190103147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY [patent_app_type] => utility [patent_app_number] => 16/190627 [patent_app_country] => US [patent_app_date] => 2018-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16190627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/190627
Apparatuses and methods for targeted refreshing of memory Nov 13, 2018 Issued
Array ( [id] => 16047673 [patent_doc_number] => 10685715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Nonvolatile semiconductor memory device which performs improved erase operation [patent_app_type] => utility [patent_app_number] => 16/180541 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6038 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180541 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180541
Nonvolatile semiconductor memory device which performs improved erase operation Nov 4, 2018 Issued
Array ( [id] => 16479338 [patent_doc_number] => 10854291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Backup and/or restore of a memory circuit [patent_app_type] => utility [patent_app_number] => 16/167822 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10005 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167822 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/167822
Backup and/or restore of a memory circuit Oct 22, 2018 Issued
Array ( [id] => 16047669 [patent_doc_number] => 10685713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Storage device including nonvolatile memory device and controller [patent_app_type] => utility [patent_app_number] => 16/163968 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 11999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/163968
Storage device including nonvolatile memory device and controller Oct 17, 2018 Issued
Array ( [id] => 15672515 [patent_doc_number] => 10600496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-24 [patent_title] => Modifying memory bank operating parameters [patent_app_type] => utility [patent_app_number] => 16/164156 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 18546 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16164156 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/164156
Modifying memory bank operating parameters Oct 17, 2018 Issued
Array ( [id] => 14539303 [patent_doc_number] => 20190205273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => MEMORY DEVICE WITH MULTIPLE MEMORY ARRAYS TO FACILITATE IN-MEMORY COMPUTATION [patent_app_type] => utility [patent_app_number] => 16/146534 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/146534
Memory device with multiple memory arrays to facilitate in-memory computation Sep 27, 2018 Issued
Array ( [id] => 15718127 [patent_doc_number] => 20200105831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => MAGNETIC MEMORY ELEMENT WITH VOLTAGE CONTROLLED MAGNETIC ANISTROPY [patent_app_type] => utility [patent_app_number] => 16/147242 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147242 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147242
Magnetic memory element with voltage controlled magnetic anistropy Sep 27, 2018 Issued
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