Hoai V Ho

Array ( [id] => 16293306 [patent_doc_number] => 10770159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Antifuse device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/027358 [patent_app_country] => US [patent_app_date] => 2018-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16027358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15331055 [patent_doc_number] => 20200005857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => APPARATUS AND METHODS FOR TRIGGERING ROW HAMMER ADDRESS SAMPLING [patent_app_type] => utility [patent_app_number] => 16/025844 [patent_app_country] => US [patent_app_date] => 2018-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15332607 [patent_doc_number] => 20200006633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SPIN ORBIT TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY CONTAINING SHIELDING ELEMENT AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 16/024490 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16024490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16747092 [patent_doc_number] => 10972101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Level shifters, memory systems, and level shifting methods [patent_app_type] => utility [patent_app_number] => 16/023540 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4600 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16023540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17144967 [patent_doc_number] => 20210312980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => MEMORY DRIVING DEVICE [patent_app_type] => utility [patent_app_number] => 17/255993 [patent_app_country] => US [patent_app_date] => 2018-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17255993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15299473 [patent_doc_number] => 20190392872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => APPARATUSES AND METHODS FOR REDUCING ROW ADDRESS TO COLUMN ADDRESS DELAY FOR A VOLTAGE THRESHOLD COMPENSATION SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 16/017826 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15299513 [patent_doc_number] => 20190392892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => MEMORY DEVICE WITH ENHANCED ACCESS CAPABILITY AND ASSOCIATED METHOD [patent_app_type] => utility [patent_app_number] => 16/017600 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14691115 [patent_doc_number] => 20190244673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => DYNAMIC ERASE LOOP DEPENDENT BIAS VOLTAGE [patent_app_type] => utility [patent_app_number] => 16/017996 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13832133 [patent_doc_number] => 20190019551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/016548 [patent_app_country] => US [patent_app_date] => 2018-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16016548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14671555 [patent_doc_number] => 10373692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Memory system performing read of nonvolatile semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/982024 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 11891 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13528431 [patent_doc_number] => 20180315758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SUBSTRATE PROCESSING METHOD AND DEVICE MANUFACTURED USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/951644 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15138903 [patent_doc_number] => 10482933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Column multiplexor decoding [patent_app_type] => utility [patent_app_number] => 15/951426 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3754 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14706633 [patent_doc_number] => 10381074 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors [patent_app_type] => utility [patent_app_number] => 15/949564 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15474785 [patent_doc_number] => 10553275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Device having write assist circuit including memory-adapted transistors and method for making the same [patent_app_type] => utility [patent_app_number] => 15/949774 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 16910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15519461 [patent_doc_number] => 10566329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Semiconductor device having data signal path of meandering shape via a plurality of wirings [patent_app_type] => utility [patent_app_number] => 15/925762 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6640 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15925762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14078891 [patent_doc_number] => 20190088333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/916538 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15315035 [patent_doc_number] => 10522227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Semiconductor memory device applying different voltages to respective select gate lines [patent_app_type] => utility [patent_app_number] => 15/916404 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7104 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14078905 [patent_doc_number] => 20190088340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/916472 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16210559 [patent_doc_number] => 20200243549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => FERROELECTRIC MEMORY IC AS WELL AS METHOD OF OPERATING THE SAME AND METHOD OF PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/322032 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16210559 [patent_doc_number] => 20200243549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => FERROELECTRIC MEMORY IC AS WELL AS METHOD OF OPERATING THE SAME AND METHOD OF PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/322032 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322032 [rel_patent_id] =>[rel_patent_doc_number] =>)