Hoai V. Ho

Array ( [id] => 13188299 [patent_doc_number] => 10109677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Select device for memory cell applications [patent_app_type] => utility [patent_app_number] => 15/665577 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12054284 [patent_doc_number] => 20170330629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION' [patent_app_type] => utility [patent_app_number] => 15/666114 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6145 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15666114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13131613 [patent_doc_number] => 10083745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Apparatuses, devices and methods for sensing a snapback event in a circuit [patent_app_type] => utility [patent_app_number] => 15/664467 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5681 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15664467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12033571 [patent_doc_number] => 20170323670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'SENSE AMPLIFIER' [patent_app_type] => utility [patent_app_number] => 15/657408 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4683 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13173597 [patent_doc_number] => 10102918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Semiconductor device, for reading fuse data using a command, semiconductor system and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/656138 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13769011 [patent_doc_number] => 10176852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Semiconductor memory devices, methods of operation, and memory systems having reduced decoder width and core skew [patent_app_type] => utility [patent_app_number] => 15/656050 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 11584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13228395 [patent_doc_number] => 10127976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Static random access memory cell array, static random access memory cell and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/655914 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15109311 [patent_doc_number] => 10475988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => High efficiency spin torque switching using a ferrimagnet [patent_app_type] => utility [patent_app_number] => 15/656848 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 2665 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12033577 [patent_doc_number] => 20170323675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY' [patent_app_type] => utility [patent_app_number] => 15/656084 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15656084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14125023 [patent_doc_number] => 10249374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Voltage supply circuit and semiconductor storage device [patent_app_type] => utility [patent_app_number] => 15/623759 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5601 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11983390 [patent_doc_number] => 20170287545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING PDA FUNCTION' [patent_app_type] => utility [patent_app_number] => 15/624511 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7990 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14204615 [patent_doc_number] => 10269426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Integrated circuits with complementary non-volatile resistive memory elements [patent_app_type] => utility [patent_app_number] => 15/624413 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7285 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13819073 [patent_doc_number] => 10186309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Methods of operating semiconductor memory devices and semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 15/624491 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8636 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15624491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13056647 [patent_doc_number] => 10049719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-14 [patent_title] => Voltage system and method for operating the same [patent_app_type] => utility [patent_app_number] => 15/620212 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5745 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13018813 [patent_doc_number] => 10032522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Three-transistor OTP memory cell [patent_app_type] => utility [patent_app_number] => 15/620657 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3026 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14557727 [patent_doc_number] => 10347331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Read threshold optimization in flash memories [patent_app_type] => utility [patent_app_number] => 15/620179 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6429 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15620179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12129919 [patent_doc_number] => 20180013505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'DATA PROCESSING DEVICE AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 15/619843 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8922 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030763 [patent_doc_number] => 10038005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-31 [patent_title] => Sense circuit having bit line clamp transistors with different threshold voltages for selectively boosting current in NAND strings [patent_app_type] => utility [patent_app_number] => 15/619791 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 35 [patent_no_of_words] => 16978 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15619791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12095305 [patent_doc_number] => 20170352399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'MEMORY MACRO AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 15/613882 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8561 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13131601 [patent_doc_number] => 10083738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Semiconductor memory device for partial erase operation and operating method of the same [patent_app_type] => utility [patent_app_number] => 15/613736 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10209 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613736 [rel_patent_id] =>[rel_patent_doc_number] =>)