
Hoai V. Ho
Examiner (ID: 15701)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2312, 2511 |
| Total Applications | 2584 |
| Issued Applications | 2371 |
| Pending Applications | 99 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10983994
[patent_doc_number] => 20160180938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 15/058828
[patent_app_country] => US
[patent_app_date] => 2016-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 14528
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058828
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/058828 | Memory system | Mar 1, 2016 | Issued |
Array
(
[id] => 10986406
[patent_doc_number] => 20160183351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'SYSTEM, METHOD, AND APPARATUS FOR POWERING INTELLIGENT LIGHTING NETWORKS'
[patent_app_type] => utility
[patent_app_number] => 15/053817
[patent_app_country] => US
[patent_app_date] => 2016-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 23956
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053817
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/053817 | SYSTEM, METHOD, AND APPARATUS FOR POWERING INTELLIGENT LIGHTING NETWORKS | Feb 24, 2016 | Abandoned |
Array
(
[id] => 10817232
[patent_doc_number] => 20160163394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-09
[patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR READING DATA FROM THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/043953
[patent_app_country] => US
[patent_app_date] => 2016-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7667
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15043953
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/043953 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR READING DATA FROM THE SAME | Feb 14, 2016 | Abandoned |
Array
(
[id] => 11659930
[patent_doc_number] => 09672941
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-06-06
[patent_title] => 'Memory element status detection'
[patent_app_type] => utility
[patent_app_number] => 15/018264
[patent_app_country] => US
[patent_app_date] => 2016-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2582
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018264
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/018264 | Memory element status detection | Feb 7, 2016 | Issued |
Array
(
[id] => 11265694
[patent_doc_number] => 09489994
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-08
[patent_title] => 'Memory timing circuit'
[patent_app_type] => utility
[patent_app_number] => 15/013605
[patent_app_country] => US
[patent_app_date] => 2016-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6062
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15013605
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/013605 | Memory timing circuit | Feb 1, 2016 | Issued |
Array
(
[id] => 11475260
[patent_doc_number] => 20170062043
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-02
[patent_title] => 'Dynamic Capacitance Balancing'
[patent_app_type] => utility
[patent_app_number] => 15/011042
[patent_app_country] => US
[patent_app_date] => 2016-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6169
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011042
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/011042 | Dynamic capacitance balancing | Jan 28, 2016 | Issued |
Array
(
[id] => 10794879
[patent_doc_number] => 20160141036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-19
[patent_title] => 'NONVOLATILE MEMORY AND RELATED REPROGRAMMING METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/007266
[patent_app_country] => US
[patent_app_date] => 2016-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7225
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007266
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/007266 | NONVOLATILE MEMORY AND RELATED REPROGRAMMING METHOD | Jan 26, 2016 | Abandoned |
Array
(
[id] => 10793460
[patent_doc_number] => 20160139618
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-19
[patent_title] => 'Induction type power supply system and intruding metal detection method thereof'
[patent_app_type] => utility
[patent_app_number] => 15/005014
[patent_app_country] => US
[patent_app_date] => 2016-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7757
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15005014
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/005014 | Induction type power supply system and intruding metal detection method thereof | Jan 24, 2016 | Issued |
Array
(
[id] => 10992844
[patent_doc_number] => 20160189790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-30
[patent_title] => 'SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR READING STORED DATA'
[patent_app_type] => utility
[patent_app_number] => 14/990090
[patent_app_country] => US
[patent_app_date] => 2016-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4672
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990090
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/990090 | Semiconductor storage device, and method for reading stored data | Jan 6, 2016 | Issued |
Array
(
[id] => 10765017
[patent_doc_number] => 20160111172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-21
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/983313
[patent_app_country] => US
[patent_app_date] => 2015-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4286
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14983313
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/983313 | SEMICONDUCTOR DEVICE | Dec 28, 2015 | Abandoned |
Array
(
[id] => 11459777
[patent_doc_number] => 20170053684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'NONVOLATILE MEMORY DEVICE FOR PERFORMING DUTY CORRECTION OPERATION, MEMORY SYSTEM, AND OPERATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/981446
[patent_app_country] => US
[patent_app_date] => 2015-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7991
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14981446
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/981446 | Nonvolatile memory device for performing duty correction operation, memory system, and operating method thereof | Dec 27, 2015 | Issued |
Array
(
[id] => 11466571
[patent_doc_number] => 09583210
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-02-28
[patent_title] => 'Fuse-based integrity protection'
[patent_app_type] => utility
[patent_app_number] => 14/978698
[patent_app_country] => US
[patent_app_date] => 2015-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 11970
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14978698
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/978698 | Fuse-based integrity protection | Dec 21, 2015 | Issued |
Array
(
[id] => 11636826
[patent_doc_number] => 09658800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-23
[patent_title] => 'End of life prediction based on memory wear'
[patent_app_type] => utility
[patent_app_number] => 14/977174
[patent_app_country] => US
[patent_app_date] => 2015-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 33
[patent_no_of_words] => 19909
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977174
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/977174 | End of life prediction based on memory wear | Dec 20, 2015 | Issued |
Array
(
[id] => 10817221
[patent_doc_number] => 20160163383
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-09
[patent_title] => 'APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE'
[patent_app_type] => utility
[patent_app_number] => 14/977411
[patent_app_country] => US
[patent_app_date] => 2015-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7901
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977411
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/977411 | Apparatuses and methods of reading memory cells based on response to a test pulse | Dec 20, 2015 | Issued |
Array
(
[id] => 13173583
[patent_doc_number] => 10102911
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-16
[patent_title] => Non-volatile semiconductor storage device for reducing the number of memory cells arranged along a control to which a memory gate voltage is applied
[patent_app_type] => utility
[patent_app_number] => 15/536167
[patent_app_country] => US
[patent_app_date] => 2015-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 28192
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 494
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15536167
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/536167 | Non-volatile semiconductor storage device for reducing the number of memory cells arranged along a control to which a memory gate voltage is applied | Dec 10, 2015 | Issued |
Array
(
[id] => 11651131
[patent_doc_number] => 20170147033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'Wearable Ring Control Device'
[patent_app_type] => utility
[patent_app_number] => 14/952764
[patent_app_country] => US
[patent_app_date] => 2015-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 2860
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952764
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/952764 | Wearable Ring Control Device | Nov 24, 2015 | Abandoned |
Array
(
[id] => 10732791
[patent_doc_number] => 20160078941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-17
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE INCLUDING A NAND STRING'
[patent_app_type] => utility
[patent_app_number] => 14/950775
[patent_app_country] => US
[patent_app_date] => 2015-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10381
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14950775
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/950775 | Semiconductor memory device including a NAND string | Nov 23, 2015 | Issued |
Array
(
[id] => 10717927
[patent_doc_number] => 20160064074
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-03
[patent_title] => 'SEMICONDUCTOR DEVICE AND INFORMATION READING METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/934630
[patent_app_country] => US
[patent_app_date] => 2015-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 16300
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14934630
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/934630 | Semiconductor device and information reading method | Nov 5, 2015 | Issued |
Array
(
[id] => 11551375
[patent_doc_number] => 09620229
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-11
[patent_title] => 'Three dimensional memory control circuitry'
[patent_app_type] => utility
[patent_app_number] => 14/926401
[patent_app_country] => US
[patent_app_date] => 2015-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8236
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926401
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/926401 | Three dimensional memory control circuitry | Oct 28, 2015 | Issued |
Array
(
[id] => 11194121
[patent_doc_number] => 09424939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-23
[patent_title] => 'Non-volatile memory apparatus and erasing method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/920895
[patent_app_country] => US
[patent_app_date] => 2015-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 4812
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920895
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/920895 | Non-volatile memory apparatus and erasing method thereof | Oct 22, 2015 | Issued |