Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13056633 [patent_doc_number] => 10049712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Semiconductor device including volatile and non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/520932 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 36 [patent_no_of_words] => 17002 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15520932 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/520932
Semiconductor device including volatile and non-volatile memory Oct 22, 2015 Issued
Array ( [id] => 11861721 [patent_doc_number] => 09741409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Apparatuses and methods for targeted refreshing of memory' [patent_app_type] => utility [patent_app_number] => 14/878354 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 12037 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878354 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/878354
Apparatuses and methods for targeted refreshing of memory Oct 7, 2015 Issued
Array ( [id] => 10681338 [patent_doc_number] => 20160027483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/875185 [patent_app_country] => US [patent_app_date] => 2015-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5329 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875185 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/875185
Semiconductor integrated circuit with data latch control Oct 4, 2015 Issued
Array ( [id] => 14768659 [patent_doc_number] => 10395730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Non-volatile memory device with variable readout reference [patent_app_type] => utility [patent_app_number] => 15/516527 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 11091 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15516527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/516527
Non-volatile memory device with variable readout reference Sep 28, 2015 Issued
Array ( [id] => 13405069 [patent_doc_number] => 20180254077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => SELF-ALIGNED MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 15/755566 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15755566 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/755566
SELF-ALIGNED MEMORY ARRAY Sep 23, 2015 Abandoned
Array ( [id] => 11539272 [patent_doc_number] => 09613686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Management of data storage in memory cells using a non-integer number of bits per cell' [patent_app_type] => utility [patent_app_number] => 14/858313 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 12050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858313 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/858313
Management of data storage in memory cells using a non-integer number of bits per cell Sep 17, 2015 Issued
Array ( [id] => 10666753 [patent_doc_number] => 20160012898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/858120 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5557 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858120 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/858120
Memory system and programming method thereof Sep 17, 2015 Issued
Array ( [id] => 11027043 [patent_doc_number] => 20160224000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'PROGRAMMING SYSTEM FOR DEVICE CONTROL' [patent_app_type] => utility [patent_app_number] => 14/856727 [patent_app_country] => US [patent_app_date] => 2015-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4182 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14856727 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/856727
Programming system for device control Sep 16, 2015 Issued
Array ( [id] => 11346063 [patent_doc_number] => 09530475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Independently addressable memory array address spaces' [patent_app_type] => utility [patent_app_number] => 14/854418 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854418 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/854418
Independently addressable memory array address spaces Sep 14, 2015 Issued
Array ( [id] => 10495068 [patent_doc_number] => 20150380089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE WITH LINE SHARING SCHEME' [patent_app_type] => utility [patent_app_number] => 14/843616 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 19707 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14843616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/843616
Three dimensional semiconductor memory device with line sharing scheme Sep 1, 2015 Issued
Array ( [id] => 11200852 [patent_doc_number] => 09431070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-30 [patent_title] => 'Memory apparatus' [patent_app_type] => utility [patent_app_number] => 14/840054 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5527 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840054
Memory apparatus Aug 30, 2015 Issued
Array ( [id] => 11353455 [patent_doc_number] => 20160372195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'RESISTANCE RANDOM ACCESS MEMORY, OPERATING METHOD THEREOF AND OPERATING SYSTEM THEREOF' [patent_app_type] => utility [patent_app_number] => 14/838478 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2616 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14838478 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/838478
Resistance random access memory with accurate forming procedure, operating method thereof and operating system thereof Aug 27, 2015 Issued
Array ( [id] => 11431850 [patent_doc_number] => 09570170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Resistive memory device and method of operating the same' [patent_app_type] => utility [patent_app_number] => 14/839606 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 34 [patent_no_of_words] => 18388 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14839606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/839606
Resistive memory device and method of operating the same Aug 27, 2015 Issued
Array ( [id] => 11551344 [patent_doc_number] => 09620199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Semiconductor storage device having TFET access transistors and method of driving the same' [patent_app_type] => utility [patent_app_number] => 14/837424 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837424 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837424
Semiconductor storage device having TFET access transistors and method of driving the same Aug 26, 2015 Issued
Array ( [id] => 10794858 [patent_doc_number] => 20160141015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'MEMORY DEVICE INCLUDING POWER-UP CONTROL CIRCUIT, AND MEMORY SYSTEM HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/837294 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837294 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837294
Memory device including power-up control circuit, and memory system having the same Aug 26, 2015 Issued
Array ( [id] => 11452993 [patent_doc_number] => 09576641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Semiconductor device verifying signal supplied from outside' [patent_app_type] => utility [patent_app_number] => 14/836315 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 12971 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836315 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/836315
Semiconductor device verifying signal supplied from outside Aug 25, 2015 Issued
Array ( [id] => 10479187 [patent_doc_number] => 20150364204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, EXTERNAL POWER CONTROLLING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/835230 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6501 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835230 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835230
Nonvolatile memory device, memory system having the same, external power controlling method thereof Aug 24, 2015 Issued
Array ( [id] => 10479165 [patent_doc_number] => 20150364182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGURABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK COLOCATED WITH A MEMORY MODULE OR SUBSYSTEM' [patent_app_type] => utility [patent_app_number] => 14/834273 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5457 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14834273 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/834273
System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem Aug 23, 2015 Issued
Array ( [id] => 10472026 [patent_doc_number] => 20150357042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/829750 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6790 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829750 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/829750
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Aug 18, 2015 Abandoned
Array ( [id] => 10472036 [patent_doc_number] => 20150357052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/830482 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9303 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830482 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/830482
SEMICONDUCTOR MEMORY DEVICE Aug 18, 2015 Abandoned
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