Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11246206 [patent_doc_number] => 09472252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Apparatuses and methods for improving retention performance of hierarchical digit lines' [patent_app_type] => utility [patent_app_number] => 13/843209 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3751 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13843209 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/843209
Apparatuses and methods for improving retention performance of hierarchical digit lines Mar 14, 2013 Issued
Array ( [id] => 9571546 [patent_doc_number] => 20140189258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/834251 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834251 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/834251
Semiconductor memory device Mar 14, 2013 Issued
Array ( [id] => 10871855 [patent_doc_number] => 08897067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Nonvolatile memory cells and methods of making such cells' [patent_app_type] => utility [patent_app_number] => 13/795036 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5744 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795036 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795036
Nonvolatile memory cells and methods of making such cells Mar 11, 2013 Issued
Array ( [id] => 8938622 [patent_doc_number] => 20130188419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-25 [patent_title] => 'MEMORY WITH SEPARATE READ AND WRITE PATHS' [patent_app_type] => utility [patent_app_number] => 13/785525 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9534 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785525 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785525
Memory with separate read and write paths Mar 4, 2013 Issued
Array ( [id] => 8926752 [patent_doc_number] => 20130182512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'MEMORY CIRCUITS HAVING A PLURALITY OF KEEPERS' [patent_app_type] => utility [patent_app_number] => 13/786103 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786103
Memory circuits having a plurality of keepers Mar 4, 2013 Issued
Array ( [id] => 8915140 [patent_doc_number] => 20130176765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'ONE-TIME PROGRAMABLE CELL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME, AND DATA JUDGING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/780683 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7542 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13780683 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/780683
One-time programmable cell circuit, semiconductor integrated circuit including the same, and data judging method thereof Feb 27, 2013 Issued
Array ( [id] => 9640890 [patent_doc_number] => 20140219001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'APPLYING A BIAS SIGNAL TO MEMORY CELLS TO REVERSE A RESISTANCE SHIFT OF THE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 13/761301 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761301
Applying a bias signal to memory cells to reverse a resistance shift of the memory cells Feb 6, 2013 Issued
Array ( [id] => 9640890 [patent_doc_number] => 20140219001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'APPLYING A BIAS SIGNAL TO MEMORY CELLS TO REVERSE A RESISTANCE SHIFT OF THE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 13/761301 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761301
Applying a bias signal to memory cells to reverse a resistance shift of the memory cells Feb 6, 2013 Issued
Array ( [id] => 9640891 [patent_doc_number] => 20140219003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'Temperature Based Logic Profile for Variable Resistance Memory Cells' [patent_app_type] => utility [patent_app_number] => 13/761975 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761975 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761975
Temperature based logic profile for variable resistance memory cells Feb 6, 2013 Issued
Array ( [id] => 9640890 [patent_doc_number] => 20140219001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'APPLYING A BIAS SIGNAL TO MEMORY CELLS TO REVERSE A RESISTANCE SHIFT OF THE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 13/761301 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761301
Applying a bias signal to memory cells to reverse a resistance shift of the memory cells Feb 6, 2013 Issued
Array ( [id] => 9640890 [patent_doc_number] => 20140219001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'APPLYING A BIAS SIGNAL TO MEMORY CELLS TO REVERSE A RESISTANCE SHIFT OF THE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 13/761301 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761301 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761301
Applying a bias signal to memory cells to reverse a resistance shift of the memory cells Feb 6, 2013 Issued
Array ( [id] => 9640918 [patent_doc_number] => 20140219029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'PROGRAMMING METHOD FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/760969 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2953 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760969 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760969
Nonvolatile semiconductor memory device programmable via overlapping pulse signals Feb 5, 2013 Issued
Array ( [id] => 8864731 [patent_doc_number] => 20130148434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/760261 [patent_app_country] => US [patent_app_date] => 2013-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12178 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760261 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/760261
Semiconductor memory device and data write method thereof Feb 5, 2013 Issued
Array ( [id] => 10603829 [patent_doc_number] => 09324398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Apparatuses and methods for targeted refreshing of memory' [patent_app_type] => utility [patent_app_number] => 13/758667 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 12088 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758667 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758667
Apparatuses and methods for targeted refreshing of memory Feb 3, 2013 Issued
Array ( [id] => 9945851 [patent_doc_number] => 08995167 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-31 [patent_title] => 'Reverse program and erase cycling algorithms' [patent_app_type] => utility [patent_app_number] => 13/757275 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9681 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757275 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/757275
Reverse program and erase cycling algorithms Jan 31, 2013 Issued
Array ( [id] => 9819349 [patent_doc_number] => 08929144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/755419 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755419 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755419
Nonvolatile semiconductor memory device Jan 30, 2013 Issued
Array ( [id] => 9475777 [patent_doc_number] => 20140133240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'SOLID STATE STORAGE DEVICE WITH SLEEP CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/753621 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6844 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753621 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753621
Solid state storage device with sleep control circuit Jan 29, 2013 Issued
Array ( [id] => 9890302 [patent_doc_number] => 08976569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Mitigation of inoperable low resistance elements in programable crossbar arrays' [patent_app_type] => utility [patent_app_number] => 13/754431 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13754431 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/754431
Mitigation of inoperable low resistance elements in programable crossbar arrays Jan 29, 2013 Issued
Array ( [id] => 8949090 [patent_doc_number] => 20130194870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/750935 [patent_app_country] => US [patent_app_date] => 2013-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13750935 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/750935
Semiconductor memory device including memory cells and a peripheral circuit and method of operating the same Jan 24, 2013 Issued
Array ( [id] => 9614801 [patent_doc_number] => 20140204658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'Memory Cell Flipping for Mitigating SRAM BTI' [patent_app_type] => utility [patent_app_number] => 13/749672 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13749672 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/749672
Memory cell flipping for mitigating SRAM BTI Jan 23, 2013 Issued
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