
Hoai V. Ho
Examiner (ID: 15701)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2312, 2511 |
| Total Applications | 2584 |
| Issued Applications | 2371 |
| Pending Applications | 99 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10195574
[patent_doc_number] => 09224487
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-29
[patent_title] => 'Semiconductor memory read and write access'
[patent_app_type] => utility
[patent_app_number] => 13/749246
[patent_app_country] => US
[patent_app_date] => 2013-01-24
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 12441
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13749246
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/749246 | Semiconductor memory read and write access | Jan 23, 2013 | Issued |
Array
(
[id] => 9033037
[patent_doc_number] => 20130235675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-12
[patent_title] => 'OUTPUT DRIVING CIRCUIT CAPABLE OF DECREASING NOISE, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/747710
[patent_app_country] => US
[patent_app_date] => 2013-01-23
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13747710
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/747710 | Output driving circuit capable of decreasing noise, and semiconductor memory device including the same | Jan 22, 2013 | Issued |
Array
(
[id] => 10518559
[patent_doc_number] => 09245612
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[patent_kind] => B2
[patent_issue_date] => 2016-01-26
[patent_title] => 'Semiconductor device having bit lines hierarchically structured'
[patent_app_type] => utility
[patent_app_number] => 13/748433
[patent_app_country] => US
[patent_app_date] => 2013-01-23
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/748433 | Semiconductor device having bit lines hierarchically structured | Jan 22, 2013 | Issued |
Array
(
[id] => 9705676
[patent_doc_number] => 08830756
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[patent_kind] => B2
[patent_issue_date] => 2014-09-09
[patent_title] => 'Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory'
[patent_app_type] => utility
[patent_app_number] => 13/747504
[patent_app_country] => US
[patent_app_date] => 2013-01-23
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/747504 | Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory | Jan 22, 2013 | Issued |
Array
(
[id] => 9614803
[patent_doc_number] => 20140204660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-24
[patent_title] => 'MEMORY HAVING SENSE AMPLIFIER FOR OUTPUT TRACKING BY CONTROLLED FEEDBACK LATCH'
[patent_app_type] => utility
[patent_app_number] => 13/747814
[patent_app_country] => US
[patent_app_date] => 2013-01-23
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/747814 | Memory having sense amplifier for output tracking by controlled feedback latch | Jan 22, 2013 | Issued |
Array
(
[id] => 9614826
[patent_doc_number] => 20140204683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-24
[patent_title] => 'MARGIN FREE PVT TOLERANT FAST SELF-TIMED SENSE AMPLIFIER RESET CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/748082
[patent_app_country] => US
[patent_app_date] => 2013-01-23
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748082
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/748082 | Margin free PVT tolerant fast self-timed sense amplifier reset circuit | Jan 22, 2013 | Issued |
Array
(
[id] => 10893904
[patent_doc_number] => 08917530
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-23
[patent_title] => 'Probabilistically-banked content addressable memory and storage'
[patent_app_type] => utility
[patent_app_number] => 13/747166
[patent_app_country] => US
[patent_app_date] => 2013-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/747166 | Probabilistically-banked content addressable memory and storage | Jan 21, 2013 | Issued |
Array
(
[id] => 9080303
[patent_doc_number] => 20130265833
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-10
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/747200
[patent_app_country] => US
[patent_app_date] => 2013-01-22
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13747200
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/747200 | Semiconductor device and method of operating the same | Jan 21, 2013 | Issued |
Array
(
[id] => 9601901
[patent_doc_number] => 20140198583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-17
[patent_title] => 'Method and System for Reducing the Size of Nonvolatile Memories'
[patent_app_type] => utility
[patent_app_number] => 13/743409
[patent_app_country] => US
[patent_app_date] => 2013-01-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/743409 | Method and System for Reducing the Size of Nonvolatile Memories | Jan 16, 2013 | Abandoned |
Array
(
[id] => 9939107
[patent_doc_number] => 08988926
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[patent_kind] => B2
[patent_issue_date] => 2015-03-24
[patent_title] => 'Method, system and device for phase change memory with shunt'
[patent_app_type] => utility
[patent_app_number] => 13/739387
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[patent_app_date] => 2013-01-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/739387 | Method, system and device for phase change memory with shunt | Jan 10, 2013 | Issued |
Array
(
[id] => 10839589
[patent_doc_number] => 08867274
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-21
[patent_title] => 'Method of operating nonvolatile memory device controlled by controlling coupling resistance value between bit line and page buffer'
[patent_app_type] => utility
[patent_app_number] => 13/726861
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[patent_app_date] => 2012-12-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/726861 | Method of operating nonvolatile memory device controlled by controlling coupling resistance value between bit line and page buffer | Dec 25, 2012 | Issued |
Array
(
[id] => 9824796
[patent_doc_number] => 08934289
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[patent_issue_date] => 2015-01-13
[patent_title] => 'Multiple bit nonvolatile memory based on current induced domain wall motion in a nanowire magnetic tunnel junction'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/689934 | Multiple bit nonvolatile memory based on current induced domain wall motion in a nanowire magnetic tunnel junction | Nov 29, 2012 | Issued |
Array
(
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[patent_title] => 'Control of inputs to a memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/683313 | Control of inputs to a memory device | Nov 20, 2012 | Issued |
Array
(
[id] => 10859217
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[patent_title] => 'Integrated circuit and memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/672140 | Integrated circuit and memory device | Nov 7, 2012 | Issued |
Array
(
[id] => 10877875
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[patent_issue_date] => 2014-12-02
[patent_title] => 'Flash memory with data retention bias'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/672184 | Flash memory with data retention bias | Nov 7, 2012 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/672408 | Integrated circuit including e-fuse array circuit | Nov 7, 2012 | Issued |
Array
(
[id] => 8813285
[patent_doc_number] => 20130114330
[patent_country] => US
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[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/671590 | Semiconductor memory device including amplifier circuit | Nov 7, 2012 | Issued |
Array
(
[id] => 8706718
[patent_doc_number] => 20130064007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-14
[patent_title] => 'DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 13/671281
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/671281 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL | Nov 6, 2012 | Abandoned |
Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/670802 | Semiconductor device performing refresh operation | Nov 6, 2012 | Issued |