Hoai V. Ho

Array ( [id] => 9185418 [patent_doc_number] => 08625364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Semiconductor memory devices and systems including data output circuits to output stored data during first output mode and output programmed data pattern during second output mode' [patent_app_type] => utility [patent_app_number] => 13/482536 [patent_app_country] => US [patent_app_date] => 2012-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4614 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13482536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8392258 [patent_doc_number] => 20120230100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'PROGRAMMABLE PHASE-CHANGE MEMORY AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/481030 [patent_app_country] => US [patent_app_date] => 2012-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3371 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13481030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9274686 [patent_doc_number] => 08638628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Maintenance of amplified signals using high-voltage-threshold transistors' [patent_app_type] => utility [patent_app_number] => 13/480701 [patent_app_country] => US [patent_app_date] => 2012-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13480701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8809135 [patent_doc_number] => 08446794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Refreshing data of memory cells with electrically floating body transistors' [patent_app_type] => utility [patent_app_number] => 13/479065 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 14027 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8809135 [patent_doc_number] => 08446794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Refreshing data of memory cells with electrically floating body transistors' [patent_app_type] => utility [patent_app_number] => 13/479065 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 14027 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8440853 [patent_doc_number] => 20120257469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'Leakage and NBTI Reduction Technique for Memory' [patent_app_type] => utility [patent_app_number] => 13/474377 [patent_app_country] => US [patent_app_date] => 2012-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11791 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8415798 [patent_doc_number] => 20120243298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'METHOD AND APPARATUS PROVIDING A CROSS-POINT MEMORY ARRAY USING A VARIABLE RESISTANCE MEMORY CELL AND CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 13/467563 [patent_app_country] => US [patent_app_date] => 2012-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2907 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13467563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8440848 [patent_doc_number] => 20120257465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'Non-volatile Memory Device With Plural Reference Cells, And Method Of Setting The Reference Cells' [patent_app_type] => utility [patent_app_number] => 13/466872 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4226 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9591086 [patent_doc_number] => 08780639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Non-volatile memory device with plural reference cells, and method of setting the reference cells' [patent_app_type] => utility [patent_app_number] => 13/466878 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4226 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9240711 [patent_doc_number] => 08605508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Non-volatile semiconductor storage device having control circuit to control voltages to select transistor for erase operation' [patent_app_type] => utility [patent_app_number] => 13/463889 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 37 [patent_no_of_words] => 17398 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10125016 [patent_doc_number] => 09159381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Tunable reference circuit' [patent_app_type] => utility [patent_app_number] => 13/464242 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14295 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9779662 [patent_doc_number] => 08854876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Perpendicular magnetization storage element and storage device' [patent_app_type] => utility [patent_app_number] => 13/462538 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8867 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13462538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9819345 [patent_doc_number] => 08929140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Memory system in which a read level is changed based on standing time and at least one of a read, write or erase count' [patent_app_type] => utility [patent_app_number] => 13/462022 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 11913 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13462022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8494651 [patent_doc_number] => 20120294059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'STACKED MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/462338 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13462338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8890163 [patent_doc_number] => 20130163347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/461144 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4285 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8975126 [patent_doc_number] => 20130208556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'Power-On-Reset (POR) Circuits for Resetting Memory Devices, and Related Circuits, Systems, and Methods' [patent_app_type] => utility [patent_app_number] => 13/460862 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7790 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9119812 [patent_doc_number] => 20130286734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'NAND FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 13/460256 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 8545 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8482063 [patent_doc_number] => 20120281470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/459724 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8482049 [patent_doc_number] => 20120281456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/459566 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 23235 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9356888 [patent_doc_number] => 08675434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-18 [patent_title] => 'High speed time interleaved sense amplifier circuits, methods and memory devices incorporating the same' [patent_app_type] => utility [patent_app_number] => 13/459206 [patent_app_country] => US [patent_app_date] => 2012-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459206 [rel_patent_id] =>[rel_patent_doc_number] =>)