Hoai V. Ho

Array ( [id] => 4601662 [patent_doc_number] => 07978500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance' [patent_app_type] => utility [patent_app_number] => 12/688229 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2973 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978500.pdf [firstpage_image] =>[orig_patent_app_number] => 12688229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7520031 [patent_doc_number] => 07974136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio' [patent_app_type] => utility [patent_app_number] => 12/645337 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3238 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/974/07974136.pdf [firstpage_image] =>[orig_patent_app_number] => 12645337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6589389 [patent_doc_number] => 20100097864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/645104 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11399 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097864.pdf [firstpage_image] =>[orig_patent_app_number] => 12645104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6589259 [patent_doc_number] => 20100097856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'FLASH MEMORY AND ASSOCIATED METHODS' [patent_app_type] => utility [patent_app_number] => 12/643610 [patent_app_country] => US [patent_app_date] => 2009-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097856.pdf [firstpage_image] =>[orig_patent_app_number] => 12643610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6470590 [patent_doc_number] => 20100091594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'SEMICONDUCTOR MEMORY FOR DISCONNECTING A BIT LINE FROM SENSE AMPLIFIER IN A STANDBY PERIOD AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/641469 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 22563 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091594.pdf [firstpage_image] =>[orig_patent_app_number] => 12641469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6180932 [patent_doc_number] => 20110122674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'REVERSE CONNECTION MTJ CELL FOR STT MRAM' [patent_app_type] => utility [patent_app_number] => 12/626092 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20110122674.pdf [firstpage_image] =>[orig_patent_app_number] => 12626092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6181022 [patent_doc_number] => 20110122695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'PROGRAMMING MEMORY WITH BIT LINE FLOATING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING' [patent_app_type] => utility [patent_app_number] => 12/624584 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 25891 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20110122695.pdf [firstpage_image] =>[orig_patent_app_number] => 12624584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8387478 [patent_doc_number] => 08264881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Semiconductor memory including pads coupled to each other' [patent_app_type] => utility [patent_app_number] => 12/624764 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11606 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12624764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7812350 [patent_doc_number] => 08134885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'High-speed compression architecture for memory' [patent_app_type] => utility [patent_app_number] => 12/625034 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/134/08134885.pdf [firstpage_image] =>[orig_patent_app_number] => 12625034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8234109 [patent_doc_number] => 08199566 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-12 [patent_title] => 'Write performance of phase change memory using set-pulse shaping' [patent_app_type] => utility [patent_app_number] => 12/623926 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/199/08199566.pdf [firstpage_image] =>[orig_patent_app_number] => 12623926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6243192 [patent_doc_number] => 20100135056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/622864 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4916 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20100135056.pdf [firstpage_image] =>[orig_patent_app_number] => 12622864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8387496 [patent_doc_number] => 08264899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Assistance in reset of data storage array' [patent_app_type] => utility [patent_app_number] => 12/621660 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2859 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12621660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7754150 [patent_doc_number] => 08111576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'High-voltage sawtooth current driving circuit and memory device including same' [patent_app_type] => utility [patent_app_number] => 12/620760 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4533 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/111/08111576.pdf [firstpage_image] =>[orig_patent_app_number] => 12620760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6618307 [patent_doc_number] => 20100172189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/620986 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 17334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20100172189.pdf [firstpage_image] =>[orig_patent_app_number] => 12620986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7765530 [patent_doc_number] => 08116164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/621014 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5264 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/116/08116164.pdf [firstpage_image] =>[orig_patent_app_number] => 12621014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6530707 [patent_doc_number] => 20100124141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE OF DUAL-PORT TYPE' [patent_app_type] => utility [patent_app_number] => 12/620276 [patent_app_country] => US [patent_app_date] => 2009-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7364 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124141.pdf [firstpage_image] =>[orig_patent_app_number] => 12620276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8204648 [patent_doc_number] => 08189408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Memory device having shifting capability and method thereof' [patent_app_type] => utility [patent_app_number] => 12/620314 [patent_app_country] => US [patent_app_date] => 2009-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/189/08189408.pdf [firstpage_image] =>[orig_patent_app_number] => 12620314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6564747 [patent_doc_number] => 20100128535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'SEMICONDUCTOR MEMORY AND METHOD AND SYSTEM FOR ACTUATING SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/620172 [patent_app_country] => US [patent_app_date] => 2009-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15379 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128535.pdf [firstpage_image] =>[orig_patent_app_number] => 12620172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6053788 [patent_doc_number] => 20110110148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'MEMORY ARRAYS AND ASSOCIATED METHODS OF MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 12/617501 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5093 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20110110148.pdf [firstpage_image] =>[orig_patent_app_number] => 12617501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6218975 [patent_doc_number] => 20100054070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'METHOD AND SYSTEM FOR CONTROLLING REFRESH TO AVOID MEMORY CELL DATA LOSSES' [patent_app_type] => utility [patent_app_number] => 12/617174 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5531 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20100054070.pdf [firstpage_image] =>[orig_patent_app_number] => 12617174 [rel_patent_id] =>[rel_patent_doc_number] =>)