Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4467893 [patent_doc_number] => 07936610 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-03 [patent_title] => 'Selective refresh of single bit memory cells' [patent_app_type] => utility [patent_app_number] => 12/534792 [patent_app_country] => US [patent_app_date] => 2009-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936610.pdf [firstpage_image] =>[orig_patent_app_number] => 12534792 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/534792
Selective refresh of single bit memory cells Aug 2, 2009 Issued
Array ( [id] => 8330076 [patent_doc_number] => 08238146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Variable integrated analog resistor' [patent_app_type] => utility [patent_app_number] => 12/534818 [patent_app_country] => US [patent_app_date] => 2009-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12534818 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/534818
Variable integrated analog resistor Aug 2, 2009 Issued
Array ( [id] => 5484222 [patent_doc_number] => 20090273987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/502374 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3996 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273987.pdf [firstpage_image] =>[orig_patent_app_number] => 12502374 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502374
Data output circuit Jul 13, 2009 Issued
Array ( [id] => 6133075 [patent_doc_number] => 20110007546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'Anti-Parallel Diode Structure and Method of Fabrication' [patent_app_type] => utility [patent_app_number] => 12/501796 [patent_app_country] => US [patent_app_date] => 2009-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4225 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20110007546.pdf [firstpage_image] =>[orig_patent_app_number] => 12501796 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/501796
Anti-parallel diode structure and method of fabrication Jul 12, 2009 Issued
Array ( [id] => 5484205 [patent_doc_number] => 20090273970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'MEMORY DEVICE INCLUDING A PROGRAMMABLE RESISTANCE ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/500673 [patent_app_country] => US [patent_app_date] => 2009-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5782 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273970.pdf [firstpage_image] =>[orig_patent_app_number] => 12500673 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500673
Memory device including a programmable resistance element Jul 9, 2009 Issued
Array ( [id] => 6337813 [patent_doc_number] => 20100329062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Leakage and NBTI Reduction Technique for Memory' [patent_app_type] => utility [patent_app_number] => 12/492364 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11732 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0329/20100329062.pdf [firstpage_image] =>[orig_patent_app_number] => 12492364 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492364
Leakage and NBTI reduction technique for memory Jun 25, 2009 Issued
Array ( [id] => 6426308 [patent_doc_number] => 20100277988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'INTERNAL SOURCE VOLTAGE GENERATION CIRCUIT AND GENERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/492604 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3870 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20100277988.pdf [firstpage_image] =>[orig_patent_app_number] => 12492604 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492604
Internal source voltage generation circuit and generation method thereof Jun 25, 2009 Issued
Array ( [id] => 6227693 [patent_doc_number] => 20100182845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND METHOD FOR COPY-BACK THEREOF' [patent_app_type] => utility [patent_app_number] => 12/492446 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4471 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182845.pdf [firstpage_image] =>[orig_patent_app_number] => 12492446 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492446
Non-volatile memory device and method for copy-back thereof Jun 25, 2009 Issued
Array ( [id] => 6602640 [patent_doc_number] => 20100309718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/492434 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7158 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20100309718.pdf [firstpage_image] =>[orig_patent_app_number] => 12492434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492434
Semiconductor memory device capable of controlling a supply current of a memory cell and method thereof Jun 25, 2009 Issued
Array ( [id] => 4452847 [patent_doc_number] => 07965537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Phase change memory with finite annular conductive path' [patent_app_type] => utility [patent_app_number] => 12/491816 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3607 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965537.pdf [firstpage_image] =>[orig_patent_app_number] => 12491816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/491816
Phase change memory with finite annular conductive path Jun 24, 2009 Issued
Array ( [id] => 7718437 [patent_doc_number] => 08095759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Error management firewall in a multiprocessor computer' [patent_app_type] => utility [patent_app_number] => 12/474556 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6304 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095759.pdf [firstpage_image] =>[orig_patent_app_number] => 12474556 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/474556
Error management firewall in a multiprocessor computer May 28, 2009 Issued
Array ( [id] => 7681114 [patent_doc_number] => 20100023694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'Memory access system, memory control apparatus, memory control method and program' [patent_app_type] => utility [patent_app_number] => 12/453953 [patent_app_country] => US [patent_app_date] => 2009-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9051 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023694.pdf [firstpage_image] =>[orig_patent_app_number] => 12453953 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453953
Memory access system, memory control apparatus, memory control method and program May 27, 2009 Issued
Array ( [id] => 8087403 [patent_doc_number] => 08151033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Mechanism for virtual logical volume management' [patent_app_type] => utility [patent_app_number] => 12/473854 [patent_app_country] => US [patent_app_date] => 2009-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151033.pdf [firstpage_image] =>[orig_patent_app_number] => 12473854 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/473854
Mechanism for virtual logical volume management May 27, 2009 Issued
Array ( [id] => 6413352 [patent_doc_number] => 20100306477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'STORE PREFETCHING VIA STORE QUEUE LOOKAHEAD' [patent_app_type] => utility [patent_app_number] => 12/473989 [patent_app_country] => US [patent_app_date] => 2009-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306477.pdf [firstpage_image] =>[orig_patent_app_number] => 12473989 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/473989
Store prefetching via store queue lookahead May 27, 2009 Issued
Array ( [id] => 6413518 [patent_doc_number] => 20100306494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'DYNAMICALLY ALLOCATING LIMITED SYSTEM MEMORY FOR DMA AMONG MULTIPLE ADAPTERS' [patent_app_type] => utility [patent_app_number] => 12/473573 [patent_app_country] => US [patent_app_date] => 2009-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 13264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306494.pdf [firstpage_image] =>[orig_patent_app_number] => 12473573 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/473573
Dynamically allocating limited system memory for DMA among multiple adapters May 27, 2009 Issued
Array ( [id] => 8030851 [patent_doc_number] => 08144517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Multilayered nonvolatile memory with adaptive control' [patent_app_type] => utility [patent_app_number] => 12/472033 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5701 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/144/08144517.pdf [firstpage_image] =>[orig_patent_app_number] => 12472033 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/472033
Multilayered nonvolatile memory with adaptive control May 25, 2009 Issued
Array ( [id] => 5317590 [patent_doc_number] => 20090282188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'MEMORY DEVICE AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/470552 [patent_app_country] => US [patent_app_date] => 2009-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4277 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282188.pdf [firstpage_image] =>[orig_patent_app_number] => 12470552 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/470552
Memory device and control method May 21, 2009 Issued
Array ( [id] => 5489357 [patent_doc_number] => 20090290428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'READ/VERIFICATION REFERENCE VOLTAGE SUPPLY UNIT OF NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/468250 [patent_app_country] => US [patent_app_date] => 2009-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3890 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20090290428.pdf [firstpage_image] =>[orig_patent_app_number] => 12468250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/468250
READ/VERIFICATION REFERENCE VOLTAGE SUPPLY UNIT OF NONVOLATILE MEMORY DEVICE May 18, 2009 Abandoned
Array ( [id] => 5551049 [patent_doc_number] => 20090285035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Pipelined wordline memory architecture' [patent_app_type] => utility [patent_app_number] => 12/468046 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1117 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20090285035.pdf [firstpage_image] =>[orig_patent_app_number] => 12468046 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/468046
Pipelined wordline memory architecture May 17, 2009 Abandoned
Array ( [id] => 4438920 [patent_doc_number] => 07898900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Latency counter, semiconductor memory device including the same, and data processing system' [patent_app_type] => utility [patent_app_number] => 12/467620 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8795 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898900.pdf [firstpage_image] =>[orig_patent_app_number] => 12467620 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467620
Latency counter, semiconductor memory device including the same, and data processing system May 17, 2009 Issued
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