Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5433899 [patent_doc_number] => 20090168485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'PIPE LATCH DEVICE OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/398583 [patent_app_country] => US [patent_app_date] => 2009-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6084 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168485.pdf [firstpage_image] =>[orig_patent_app_number] => 12398583 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/398583
Pipe latch device of semiconductor memory device Mar 4, 2009 Issued
Array ( [id] => 5513355 [patent_doc_number] => 20090213661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'NON-VOLATILE MEMORY DEVICE ADAPTED TO REDUCE COUPLING EFFECT BETWEEN STORAGE ELEMENTS AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 12/396147 [patent_app_country] => US [patent_app_date] => 2009-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7363 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20090213661.pdf [firstpage_image] =>[orig_patent_app_number] => 12396147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/396147
NON-VOLATILE MEMORY DEVICE ADAPTED TO REDUCE COUPLING EFFECT BETWEEN STORAGE ELEMENTS AND RELATED METHODS Mar 1, 2009 Abandoned
Array ( [id] => 6090220 [patent_doc_number] => 20110000902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'METHOD AND DEVICE FOR HEATING SOLUTIONS, PREFERABLY DIALYSIS SOLUTIONS' [patent_app_type] => utility [patent_app_number] => 12/735891 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2582 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20110000902.pdf [firstpage_image] =>[orig_patent_app_number] => 12735891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/735891
Method and device for heating solutions, preferably dialysis solutions Feb 26, 2009 Issued
Array ( [id] => 125538 [patent_doc_number] => 07706188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Flash memory program inhibit scheme' [patent_app_type] => utility [patent_app_number] => 12/371088 [patent_app_country] => US [patent_app_date] => 2009-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 10247 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706188.pdf [firstpage_image] =>[orig_patent_app_number] => 12371088 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/371088
Flash memory program inhibit scheme Feb 12, 2009 Issued
Array ( [id] => 4587468 [patent_doc_number] => 07835169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Semiconductor memory device and semiconductor memory system' [patent_app_type] => utility [patent_app_number] => 12/368622 [patent_app_country] => US [patent_app_date] => 2009-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7965 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/835/07835169.pdf [firstpage_image] =>[orig_patent_app_number] => 12368622 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/368622
Semiconductor memory device and semiconductor memory system Feb 9, 2009 Issued
Array ( [id] => 6508007 [patent_doc_number] => 20100202179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/366910 [patent_app_country] => US [patent_app_date] => 2009-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202179.pdf [firstpage_image] =>[orig_patent_app_number] => 12366910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/366910
Memory device with shielding plugs adjacent to a dummy word line thereof Feb 5, 2009 Issued
Array ( [id] => 6508531 [patent_doc_number] => 20100202232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'REFRESHING METHOD' [patent_app_type] => utility [patent_app_number] => 12/366916 [patent_app_country] => US [patent_app_date] => 2009-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3365 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202232.pdf [firstpage_image] =>[orig_patent_app_number] => 12366916 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/366916
Refreshing method Feb 5, 2009 Issued
Array ( [id] => 5478760 [patent_doc_number] => 20090201717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'RESISTANCE-CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/366396 [patent_app_country] => US [patent_app_date] => 2009-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20090201717.pdf [firstpage_image] =>[orig_patent_app_number] => 12366396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/366396
Resistance-change memory Feb 4, 2009 Issued
Array ( [id] => 4474638 [patent_doc_number] => 07944755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Erase verify in memory devices' [patent_app_type] => utility [patent_app_number] => 12/366216 [patent_app_country] => US [patent_app_date] => 2009-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2961 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944755.pdf [firstpage_image] =>[orig_patent_app_number] => 12366216 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/366216
Erase verify in memory devices Feb 4, 2009 Issued
Array ( [id] => 124254 [patent_doc_number] => 07710779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Nonvolatile semiconductor memory, method for reading out thereof, and memory card' [patent_app_type] => utility [patent_app_number] => 12/361362 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12998 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/710/07710779.pdf [firstpage_image] =>[orig_patent_app_number] => 12361362 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361362
Nonvolatile semiconductor memory, method for reading out thereof, and memory card Jan 27, 2009 Issued
Array ( [id] => 4559662 [patent_doc_number] => 07961503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Magnetic floating gate memory' [patent_app_type] => utility [patent_app_number] => 12/355908 [patent_app_country] => US [patent_app_date] => 2009-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3221 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961503.pdf [firstpage_image] =>[orig_patent_app_number] => 12355908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/355908
Magnetic floating gate memory Jan 18, 2009 Issued
Array ( [id] => 6368201 [patent_doc_number] => 20100080060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'DETERMINING MEMORY PAGE STATUS' [patent_app_type] => utility [patent_app_number] => 12/355934 [patent_app_country] => US [patent_app_date] => 2009-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9857 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080060.pdf [firstpage_image] =>[orig_patent_app_number] => 12355934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/355934
Determining memory page status Jan 18, 2009 Issued
Array ( [id] => 4537617 [patent_doc_number] => 07924614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Memory and boundary searching method thereof' [patent_app_type] => utility [patent_app_number] => 12/355962 [patent_app_country] => US [patent_app_date] => 2009-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3236 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/924/07924614.pdf [firstpage_image] =>[orig_patent_app_number] => 12355962 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/355962
Memory and boundary searching method thereof Jan 18, 2009 Issued
Array ( [id] => 4491850 [patent_doc_number] => 07903478 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'High impedance reference voltage distribution' [patent_app_type] => utility [patent_app_number] => 12/355466 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/903/07903478.pdf [firstpage_image] =>[orig_patent_app_number] => 12355466 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/355466
High impedance reference voltage distribution Jan 15, 2009 Issued
Array ( [id] => 4503798 [patent_doc_number] => 07948791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-24 [patent_title] => 'Memory array and method of implementing a memory array' [patent_app_type] => utility [patent_app_number] => 12/354202 [patent_app_country] => US [patent_app_date] => 2009-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6269 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948791.pdf [firstpage_image] =>[orig_patent_app_number] => 12354202 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354202
Memory array and method of implementing a memory array Jan 14, 2009 Issued
Array ( [id] => 6639667 [patent_doc_number] => 20100005253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'MEMORY CONTROLLER, PCB, COMPUTER SYSTEM AND MEMORY ADJUSTING METHOD' [patent_app_type] => utility [patent_app_number] => 12/352756 [patent_app_country] => US [patent_app_date] => 2009-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3515 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20100005253.pdf [firstpage_image] =>[orig_patent_app_number] => 12352756 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352756
Memory controller, PCB, computer system and memory adjusting method adjusting a memory output signal characteristic Jan 12, 2009 Issued
Array ( [id] => 4467972 [patent_doc_number] => 07936629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Table-based reference voltage characterization scheme' [patent_app_type] => utility [patent_app_number] => 12/352722 [patent_app_country] => US [patent_app_date] => 2009-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2795 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936629.pdf [firstpage_image] =>[orig_patent_app_number] => 12352722 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352722
Table-based reference voltage characterization scheme Jan 12, 2009 Issued
Array ( [id] => 4522343 [patent_doc_number] => 07911873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-22 [patent_title] => 'Digital delay locked loop implementation for precise control of timing signals' [patent_app_type] => utility [patent_app_number] => 12/346854 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3465 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/911/07911873.pdf [firstpage_image] =>[orig_patent_app_number] => 12346854 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346854
Digital delay locked loop implementation for precise control of timing signals Dec 30, 2008 Issued
Array ( [id] => 6600276 [patent_doc_number] => 20100032778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'MAGNETIC MEMORY WITH SEPARATE READ AND WRITE PATHS' [patent_app_type] => utility [patent_app_number] => 12/326186 [patent_app_country] => US [patent_app_date] => 2008-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20100032778.pdf [firstpage_image] =>[orig_patent_app_number] => 12326186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/326186
Magnetic memory with separate read and write paths Dec 1, 2008 Issued
Array ( [id] => 4459015 [patent_doc_number] => 07894277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith' [patent_app_type] => utility [patent_app_number] => 12/292890 [patent_app_country] => US [patent_app_date] => 2008-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 11234 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/894/07894277.pdf [firstpage_image] =>[orig_patent_app_number] => 12292890 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/292890
Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith Nov 27, 2008 Issued
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