Hoai V. Ho

Array ( [id] => 5532123 [patent_doc_number] => 20090231911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/049056 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13685 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231911.pdf [firstpage_image] =>[orig_patent_app_number] => 12049056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 64638 [patent_doc_number] => 07764565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Multi-bank block architecture for integrated circuit memory devices having non-shared sense amplifier bands between banks' [patent_app_type] => utility [patent_app_number] => 12/049244 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3388 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/764/07764565.pdf [firstpage_image] =>[orig_patent_app_number] => 12049244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 64616 [patent_doc_number] => 07764554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'I/O circuit with phase mixer for slew rate control' [patent_app_type] => utility [patent_app_number] => 12/041268 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3857 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/764/07764554.pdf [firstpage_image] =>[orig_patent_app_number] => 12041268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 46514 [patent_doc_number] => 07778065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Method and apparatus for implementing concurrent multiple level sensing operation for resistive memory devices' [patent_app_type] => utility [patent_app_number] => 12/039990 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3733 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/778/07778065.pdf [firstpage_image] =>[orig_patent_app_number] => 12039990 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4858112 [patent_doc_number] => 20080266962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/040282 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7702 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266962.pdf [firstpage_image] =>[orig_patent_app_number] => 12040282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5537971 [patent_doc_number] => 20090219776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'NON-VOLATILE MEMORY DEVICE WITH PLURAL REFERENCE CELLS, AND METHOD OF SETTING THE REFERENCE CELLS' [patent_app_type] => utility [patent_app_number] => 12/040732 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4178 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20090219776.pdf [firstpage_image] =>[orig_patent_app_number] => 12040732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15761 [patent_doc_number] => 07804735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals' [patent_app_type] => utility [patent_app_number] => 12/039908 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5724 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/804/07804735.pdf [firstpage_image] =>[orig_patent_app_number] => 12039908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4725629 [patent_doc_number] => 20080205170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'DDR-SDRAM INTERFACE CIRCUITRY, AND METHOD AND SYSTEM FOR TESTING THE INTERFACE CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 12/039316 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205170.pdf [firstpage_image] =>[orig_patent_app_number] => 12039316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 115529 [patent_doc_number] => 07715225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Memory cell using spin induced switching effects' [patent_app_type] => utility [patent_app_number] => 12/036518 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4777 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/715/07715225.pdf [firstpage_image] =>[orig_patent_app_number] => 12036518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5513344 [patent_doc_number] => 20090213650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'MIS-TRANSISTOR-BASED NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/036938 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5752 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20090213650.pdf [firstpage_image] =>[orig_patent_app_number] => 12036938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5408722 [patent_doc_number] => 20090122620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Systems and Methods for Low Power, High Yield Memory' [patent_app_type] => utility [patent_app_number] => 12/036554 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20090122620.pdf [firstpage_image] =>[orig_patent_app_number] => 12036554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4725612 [patent_doc_number] => 20080205153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD AND APPARATUS FOR CONTROLLING TWO OR MORE NON-VOLATILE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 12/036416 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3324 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205153.pdf [firstpage_image] =>[orig_patent_app_number] => 12036416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4725622 [patent_doc_number] => 20080205163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/035732 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205163.pdf [firstpage_image] =>[orig_patent_app_number] => 12035732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5513345 [patent_doc_number] => 20090213651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'TWO-BIT NON-VOLATILE FLASH MEMORY CELLS AND METHODS OF OPERATING MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 12/035786 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6702 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20090213651.pdf [firstpage_image] =>[orig_patent_app_number] => 12035786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 55584 [patent_doc_number] => 07773429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Non-volatile memory device and driving method thereof' [patent_app_type] => utility [patent_app_number] => 12/035412 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6448 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773429.pdf [firstpage_image] =>[orig_patent_app_number] => 12035412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4582503 [patent_doc_number] => 07830719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Power dependent memory access' [patent_app_type] => utility [patent_app_number] => 12/034864 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1857 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/830/07830719.pdf [firstpage_image] =>[orig_patent_app_number] => 12034864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 134064 [patent_doc_number] => 07701775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Flash memory device utilizing multi-page program method' [patent_app_type] => utility [patent_app_number] => 12/034876 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4243 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701775.pdf [firstpage_image] =>[orig_patent_app_number] => 12034876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4717332 [patent_doc_number] => 20080239854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'SEMICONDUCTOR MEMORY, SYSTEM, AND OPERATING METHOD OF SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/035248 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9636 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20080239854.pdf [firstpage_image] =>[orig_patent_app_number] => 12035248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5513362 [patent_doc_number] => 20090213668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'ADJUSTABLE PIPELINE IN A MEMORY CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/034888 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6692 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20090213668.pdf [firstpage_image] =>[orig_patent_app_number] => 12034888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5354093 [patent_doc_number] => 20090185437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'CLOCK-BASED DATA STORAGE DEVICE, DUAL PULSE GENERATION DEVICE, AND DATA STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/034556 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9287 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20090185437.pdf [firstpage_image] =>[orig_patent_app_number] => 12034556 [rel_patent_id] =>[rel_patent_doc_number] =>)