Search

Hoai V. Ho

Examiner (ID: 5108, Phone: (571)272-1777 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2312, 2818, 2511, 2827
Total Applications
2631
Issued Applications
2404
Pending Applications
100
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19444271 [patent_doc_number] => 12094558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Multiple stack high voltage circuit for memory [patent_app_type] => utility [patent_app_number] => 18/318264 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318264
Multiple stack high voltage circuit for memory May 15, 2023 Issued
Array ( [id] => 18898333 [patent_doc_number] => 20240013818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/317367 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317367
Semiconductor device May 14, 2023 Issued
Array ( [id] => 18810922 [patent_doc_number] => 20230385258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY-BASED CONTENT-ADDRESSABLE MEMORY (DRAM-CAM) ARCHITECTURE FOR EXACT PATTERN MATCHING [patent_app_type] => utility [patent_app_number] => 18/314997 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314997
Dynamic random access memory-based content-addressable memory (DRAM-CAM) architecture for exact pattern matching May 9, 2023 Issued
Array ( [id] => 19221198 [patent_doc_number] => 20240185902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => SEMICONDUCTOR SYSTEM [patent_app_type] => utility [patent_app_number] => 18/301441 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301441 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301441
Semiconductor system Apr 16, 2023 Issued
Array ( [id] => 18570240 [patent_doc_number] => 20230260577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION [patent_app_type] => utility [patent_app_number] => 18/301800 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301800 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301800
Nonvolatile semiconductor memory device which performs improved erase operation Apr 16, 2023 Issued
Array ( [id] => 18513668 [patent_doc_number] => 20230229903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SPLIT ARRAY ARCHITECTURE FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/125703 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18125703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/125703
SPLIT ARRAY ARCHITECTURE FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK Mar 22, 2023 Pending
Array ( [id] => 19399499 [patent_doc_number] => 12073885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Memory system including semiconductor memory and controller [patent_app_type] => utility [patent_app_number] => 18/121344 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6215 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121344
Memory system including semiconductor memory and controller Mar 13, 2023 Issued
Array ( [id] => 20469222 [patent_doc_number] => 12525264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Integrated multilevel memory apparatus and method of operating same for enhanced memory [patent_app_type] => utility [patent_app_number] => 18/119193 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119193 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119193
Integrated multilevel memory apparatus and method of operating same for enhanced memory Mar 7, 2023 Issued
Array ( [id] => 19842552 [patent_doc_number] => 12254951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Memory device including page buffer, memory system including page buffer, and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/173567 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 11817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/173567
Memory device including page buffer, memory system including page buffer, and operating method thereof Feb 22, 2023 Issued
Array ( [id] => 19993726 [patent_doc_number] => 20250131948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => UNDERLYING TRANSISTOR CIRCUIT OF SEMICONDUCTOR MEMORY AND PREPARATION METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 18/697495 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18697495 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/697495
Underlying transistor circuit of semiconductor memory and preparation method for the same Feb 20, 2023 Issued
Array ( [id] => 20028461 [patent_doc_number] => 20250166683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => STORAGE DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/839189 [patent_app_country] => US [patent_app_date] => 2023-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18839189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/839189
STORAGE DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING STORAGE DEVICE Feb 19, 2023 Pending
Array ( [id] => 20036038 [patent_doc_number] => 20250174260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/842463 [patent_app_country] => US [patent_app_date] => 2023-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18842463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/842463
SEMICONDUCTOR DEVICE Feb 19, 2023 Pending
Array ( [id] => 20359938 [patent_doc_number] => 12475942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Integrated circuit structure with complementary field effect transistor and memory cell and method of making thereof [patent_app_type] => utility [patent_app_number] => 18/170462 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170462 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170462
Integrated circuit structure with complementary field effect transistor and memory cell and method of making thereof Feb 15, 2023 Issued
Array ( [id] => 19054431 [patent_doc_number] => 20240096400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY DEVICE SENSE AMPLIFIER CONTROL [patent_app_type] => utility [patent_app_number] => 18/158108 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158108
Memory device sense amplifier control Jan 22, 2023 Issued
Array ( [id] => 20118221 [patent_doc_number] => 12367936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Page buffer circuit with bit line select transistor [patent_app_type] => utility [patent_app_number] => 18/157186 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2105 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157186
Page buffer circuit with bit line select transistor Jan 19, 2023 Issued
Array ( [id] => 19399532 [patent_doc_number] => 12073918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Memory device deserializer circuit with a reduced form factor [patent_app_type] => utility [patent_app_number] => 18/097668 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097668
Memory device deserializer circuit with a reduced form factor Jan 16, 2023 Issued
Array ( [id] => 18865578 [patent_doc_number] => 20230420015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => DATA RECEIVING CIRCUIT, DATA RECEIVING SYSTEM AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/154794 [patent_app_country] => US [patent_app_date] => 2023-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154794
Data receiving circuit, data receiving system and memory device Jan 13, 2023 Issued
Array ( [id] => 20080631 [patent_doc_number] => 12354706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Control apparatus, memory, signal processing method, and electronic device [patent_app_type] => utility [patent_app_number] => 18/154815 [patent_app_country] => US [patent_app_date] => 2023-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 1179 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154815
Control apparatus, memory, signal processing method, and electronic device Jan 13, 2023 Issued
Array ( [id] => 18631486 [patent_doc_number] => 20230290388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => PAGE BUFFER, MEMORY DEVICE, AND METHOD FOR PROGRAMMING THEREOF [patent_app_type] => utility [patent_app_number] => 18/096346 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096346 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096346
Page buffer, memory device, and method for programming thereof Jan 11, 2023 Issued
Array ( [id] => 18379414 [patent_doc_number] => 20230154503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => READOUT CIRCUIT, MEMORY, AND METHOD OF READING OUT DATA OF MEMORY [patent_app_type] => utility [patent_app_number] => 18/153431 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153431
Readout circuit, memory, and method of reading out data of memory Jan 11, 2023 Issued
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