
Hoai V. Ho
Examiner (ID: 15701)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2312, 2511 |
| Total Applications | 2584 |
| Issued Applications | 2371 |
| Pending Applications | 99 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5390362
[patent_doc_number] => 20090207675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'WAK Devices in SRAM Cells for Improving VCCMIN'
[patent_app_type] => utility
[patent_app_number] => 12/034416
[patent_app_country] => US
[patent_app_date] => 2008-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4120
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0207/20090207675.pdf
[firstpage_image] =>[orig_patent_app_number] => 12034416
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/034416 | WAK devices in SRAM cells for improving VCCMIN | Feb 19, 2008 | Issued |
Array
(
[id] => 85756
[patent_doc_number] => 07742324
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-22
[patent_title] => 'Systems and devices including local data lines and methods of using, making, and operating the same'
[patent_app_type] => utility
[patent_app_number] => 12/033768
[patent_app_country] => US
[patent_app_date] => 2008-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 23
[patent_no_of_words] => 8900
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/742/07742324.pdf
[firstpage_image] =>[orig_patent_app_number] => 12033768
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033768 | Systems and devices including local data lines and methods of using, making, and operating the same | Feb 18, 2008 | Issued |
Array
(
[id] => 204636
[patent_doc_number] => 07633833
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-15
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 12/028788
[patent_app_country] => US
[patent_app_date] => 2008-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 36
[patent_no_of_words] => 7825
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/633/07633833.pdf
[firstpage_image] =>[orig_patent_app_number] => 12028788
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/028788 | Semiconductor memory device | Feb 8, 2008 | Issued |
Array
(
[id] => 4544405
[patent_doc_number] => 07889558
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-15
[patent_title] => 'Nonvolatile semiconductor memory device in which an amount of data to be stored in a memory cell is allocated to every other word line units of one word line'
[patent_app_type] => utility
[patent_app_number] => 12/028480
[patent_app_country] => US
[patent_app_date] => 2008-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 20908
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/889/07889558.pdf
[firstpage_image] =>[orig_patent_app_number] => 12028480
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/028480 | Nonvolatile semiconductor memory device in which an amount of data to be stored in a memory cell is allocated to every other word line units of one word line | Feb 7, 2008 | Issued |
Array
(
[id] => 5478787
[patent_doc_number] => 20090201744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-13
[patent_title] => 'Method For Erasing A Flash Memory Cell Or An Array Of Such Cells Having Improved Erase Coupling Ratio'
[patent_app_type] => utility
[patent_app_number] => 12/027654
[patent_app_country] => US
[patent_app_date] => 2008-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3196
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20090201744.pdf
[firstpage_image] =>[orig_patent_app_number] => 12027654
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/027654 | Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio | Feb 6, 2008 | Issued |
Array
(
[id] => 179000
[patent_doc_number] => 07656711
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-02
[patent_title] => 'Semiconductor memory system including a plurality of semiconductor memory devices'
[patent_app_type] => utility
[patent_app_number] => 12/027546
[patent_app_country] => US
[patent_app_date] => 2008-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 31
[patent_no_of_words] => 11387
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/656/07656711.pdf
[firstpage_image] =>[orig_patent_app_number] => 12027546
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/027546 | Semiconductor memory system including a plurality of semiconductor memory devices | Feb 6, 2008 | Issued |
Array
(
[id] => 4811896
[patent_doc_number] => 20080192527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-14
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/027548
[patent_app_country] => US
[patent_app_date] => 2008-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4628
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0192/20080192527.pdf
[firstpage_image] =>[orig_patent_app_number] => 12027548
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/027548 | Semiconductor memory device and control method thereof | Feb 6, 2008 | Issued |
Array
(
[id] => 5478798
[patent_doc_number] => 20090201755
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-13
[patent_title] => 'MAINTENANCE OF AMPLIFIED SIGNALS USING HIGH-VOLTAGE-THRESHOLD TRANSISTORS'
[patent_app_type] => utility
[patent_app_number] => 12/027824
[patent_app_country] => US
[patent_app_date] => 2008-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2734
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20090201755.pdf
[firstpage_image] =>[orig_patent_app_number] => 12027824
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/027824 | Maintenance of amplified signals using high-voltage-threshold transistors | Feb 6, 2008 | Issued |
Array
(
[id] => 4674745
[patent_doc_number] => 20080212373
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A STACKED GATE INCLUDING A FLOATING GATE AND A CONTROL GATE'
[patent_app_type] => utility
[patent_app_number] => 12/027744
[patent_app_country] => US
[patent_app_date] => 2008-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 55
[patent_figures_cnt] => 55
[patent_no_of_words] => 30566
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20080212373.pdf
[firstpage_image] =>[orig_patent_app_number] => 12027744
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/027744 | Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate | Feb 6, 2008 | Issued |
Array
(
[id] => 197248
[patent_doc_number] => 07636268
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-12-22
[patent_title] => 'Integrated circuit with improved static noise margin'
[patent_app_type] => utility
[patent_app_number] => 12/027172
[patent_app_country] => US
[patent_app_date] => 2008-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4219
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/636/07636268.pdf
[firstpage_image] =>[orig_patent_app_number] => 12027172
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/027172 | Integrated circuit with improved static noise margin | Feb 5, 2008 | Issued |
Array
(
[id] => 74014
[patent_doc_number] => 07755943
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-13
[patent_title] => 'Unit cell block of EEPROM and semiconductor memory device having the same'
[patent_app_type] => utility
[patent_app_number] => 12/068314
[patent_app_country] => US
[patent_app_date] => 2008-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2414
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/755/07755943.pdf
[firstpage_image] =>[orig_patent_app_number] => 12068314
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/068314 | Unit cell block of EEPROM and semiconductor memory device having the same | Feb 4, 2008 | Issued |
Array
(
[id] => 4784063
[patent_doc_number] => 20080137392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => '6F2 DRAM CELL DESIGN WITH 3F-PITCH FOLDED DIGITLINE SENSE AMPLIFIER'
[patent_app_type] => utility
[patent_app_number] => 12/022451
[patent_app_country] => US
[patent_app_date] => 2008-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4407
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20080137392.pdf
[firstpage_image] =>[orig_patent_app_number] => 12022451
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/022451 | Dram cell design with folded digitline architecture and angled active areas | Jan 29, 2008 | Issued |
Array
(
[id] => 315859
[patent_doc_number] => 07525837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-28
[patent_title] => 'Magnetoresistive effect element and magnetic memory'
[patent_app_type] => utility
[patent_app_number] => 12/019657
[patent_app_country] => US
[patent_app_date] => 2008-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 6812
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 341
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/525/07525837.pdf
[firstpage_image] =>[orig_patent_app_number] => 12019657
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/019657 | Magnetoresistive effect element and magnetic memory | Jan 24, 2008 | Issued |
Array
(
[id] => 331525
[patent_doc_number] => 07512025
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-31
[patent_title] => 'Open digit line array architecture for a memory array'
[patent_app_type] => utility
[patent_app_number] => 12/009521
[patent_app_country] => US
[patent_app_date] => 2008-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6955
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/512/07512025.pdf
[firstpage_image] =>[orig_patent_app_number] => 12009521
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/009521 | Open digit line array architecture for a memory array | Jan 17, 2008 | Issued |
Array
(
[id] => 4784087
[patent_doc_number] => 20080137416
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => 'Multi bit flash memory device and method of programming the same'
[patent_app_type] => utility
[patent_app_number] => 12/000209
[patent_app_country] => US
[patent_app_date] => 2007-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8704
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20080137416.pdf
[firstpage_image] =>[orig_patent_app_number] => 12000209
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000209 | Multi bit flash memory device and method of programming the same | Dec 10, 2007 | Issued |
Array
(
[id] => 279060
[patent_doc_number] => 07558142
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'Method and system for controlling refresh to avoid memory cell data losses'
[patent_app_type] => utility
[patent_app_number] => 12/001709
[patent_app_country] => US
[patent_app_date] => 2007-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 5526
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/558/07558142.pdf
[firstpage_image] =>[orig_patent_app_number] => 12001709
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/001709 | Method and system for controlling refresh to avoid memory cell data losses | Dec 10, 2007 | Issued |
Array
(
[id] => 94753
[patent_doc_number] => 07738306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-15
[patent_title] => 'Method to improve the write speed for memory products'
[patent_app_type] => utility
[patent_app_number] => 11/999799
[patent_app_country] => US
[patent_app_date] => 2007-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8633
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 519
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/738/07738306.pdf
[firstpage_image] =>[orig_patent_app_number] => 11999799
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/999799 | Method to improve the write speed for memory products | Dec 6, 2007 | Issued |
Array
(
[id] => 125513
[patent_doc_number] => 07706173
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-27
[patent_title] => 'Memory macro composed of a plurality of memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/987536
[patent_app_country] => US
[patent_app_date] => 2007-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6088
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/706/07706173.pdf
[firstpage_image] =>[orig_patent_app_number] => 11987536
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/987536 | Memory macro composed of a plurality of memory cells | Nov 29, 2007 | Issued |
Array
(
[id] => 144248
[patent_doc_number] => 07688668
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Controlling power supply to memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/987266
[patent_app_country] => US
[patent_app_date] => 2007-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5506
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/688/07688668.pdf
[firstpage_image] =>[orig_patent_app_number] => 11987266
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/987266 | Controlling power supply to memory cells | Nov 27, 2007 | Issued |
Array
(
[id] => 135461
[patent_doc_number] => 07697356
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-13
[patent_title] => 'Method of testing semiconductor apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/987082
[patent_app_country] => US
[patent_app_date] => 2007-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2857
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/697/07697356.pdf
[firstpage_image] =>[orig_patent_app_number] => 11987082
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/987082 | Method of testing semiconductor apparatus | Nov 26, 2007 | Issued |