Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 854656 [patent_doc_number] => 07379314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-27 [patent_title] => 'Content addressable memory (CAM) architecture' [patent_app_type] => utility [patent_app_number] => 11/779347 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 9890 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/379/07379314.pdf [firstpage_image] =>[orig_patent_app_number] => 11779347 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779347
Content addressable memory (CAM) architecture Jul 17, 2007 Issued
Array ( [id] => 5224005 [patent_doc_number] => 20070253271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Refresh period generating circuit' [patent_app_type] => utility [patent_app_number] => 11/822333 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7953 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253271.pdf [firstpage_image] =>[orig_patent_app_number] => 11822333 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/822333
Refresh period generating circuit Jul 4, 2007 Issued
Array ( [id] => 346115 [patent_doc_number] => 07499306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range' [patent_app_type] => utility [patent_app_number] => 11/772569 [patent_app_country] => US [patent_app_date] => 2007-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3912 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499306.pdf [firstpage_image] =>[orig_patent_app_number] => 11772569 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772569
Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range Jul 1, 2007 Issued
Array ( [id] => 125583 [patent_doc_number] => 07706210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Semiconductor memory device including delay locked loop and method for driving the same' [patent_app_type] => utility [patent_app_number] => 11/819564 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4139 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706210.pdf [firstpage_image] =>[orig_patent_app_number] => 11819564 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819564
Semiconductor memory device including delay locked loop and method for driving the same Jun 27, 2007 Issued
Array ( [id] => 271473 [patent_doc_number] => 07564712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Flash memory device and writing method thereof' [patent_app_type] => utility [patent_app_number] => 11/769334 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564712.pdf [firstpage_image] =>[orig_patent_app_number] => 11769334 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769334
Flash memory device and writing method thereof Jun 26, 2007 Issued
Array ( [id] => 5209336 [patent_doc_number] => 20070247920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Data processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/819288 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7114 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247920.pdf [firstpage_image] =>[orig_patent_app_number] => 11819288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819288
Disk processing apparatus with voltage generating circuit having a boost ratio control Jun 25, 2007 Issued
Array ( [id] => 170836 [patent_doc_number] => 07668000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance' [patent_app_type] => utility [patent_app_number] => 11/768125 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2933 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/668/07668000.pdf [firstpage_image] =>[orig_patent_app_number] => 11768125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768125
Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance Jun 24, 2007 Issued
Array ( [id] => 4931740 [patent_doc_number] => 20080002515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'MEMORY WITH ALTERABLE COLUMN SELECTION TIME' [patent_app_type] => utility [patent_app_number] => 11/768160 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20080002515.pdf [firstpage_image] =>[orig_patent_app_number] => 11768160 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768160
MEMORY WITH ALTERABLE COLUMN SELECTION TIME Jun 24, 2007 Abandoned
Array ( [id] => 4758009 [patent_doc_number] => 20080310235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'SENSING CIRCUIT FOR MEMORIES' [patent_app_type] => utility [patent_app_number] => 11/763900 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3595 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20080310235.pdf [firstpage_image] =>[orig_patent_app_number] => 11763900 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/763900
Sensing circuit for memories Jun 14, 2007 Issued
Array ( [id] => 7726461 [patent_doc_number] => 08099741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Disk device' [patent_app_type] => utility [patent_app_number] => 12/302948 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 28219 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099741.pdf [firstpage_image] =>[orig_patent_app_number] => 12302948 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/302948
Disk device May 31, 2007 Issued
Array ( [id] => 4796406 [patent_doc_number] => 20080007992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Multi-state sense amplifier' [patent_app_type] => utility [patent_app_number] => 11/806636 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5339 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20080007992.pdf [firstpage_image] =>[orig_patent_app_number] => 11806636 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/806636
Multi-state sense amplifier May 31, 2007 Issued
Array ( [id] => 7537796 [patent_doc_number] => 08051439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Disk device' [patent_app_type] => utility [patent_app_number] => 12/303042 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 29056 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051439.pdf [firstpage_image] =>[orig_patent_app_number] => 12303042 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/303042
Disk device May 31, 2007 Issued
Array ( [id] => 300864 [patent_doc_number] => 07539071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Semiconductor device with a relief processing portion' [patent_app_type] => utility [patent_app_number] => 11/806308 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10402 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539071.pdf [firstpage_image] =>[orig_patent_app_number] => 11806308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/806308
Semiconductor device with a relief processing portion May 30, 2007 Issued
Array ( [id] => 275286 [patent_doc_number] => 07561456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Memory array including programmable poly fuses' [patent_app_type] => utility [patent_app_number] => 11/807974 [patent_app_country] => US [patent_app_date] => 2007-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5017 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/561/07561456.pdf [firstpage_image] =>[orig_patent_app_number] => 11807974 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/807974
Memory array including programmable poly fuses May 29, 2007 Issued
Array ( [id] => 4898085 [patent_doc_number] => 20080117698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'Circuit and method for a high speed dynamic RAM' [patent_app_type] => utility [patent_app_number] => 11/807520 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7408 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20080117698.pdf [firstpage_image] =>[orig_patent_app_number] => 11807520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/807520
Circuit and method for a high speed dynamic RAM May 28, 2007 Issued
Array ( [id] => 327720 [patent_doc_number] => 07515501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Memory architecture having local column select lines' [patent_app_type] => utility [patent_app_number] => 11/807272 [patent_app_country] => US [patent_app_date] => 2007-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5254 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/515/07515501.pdf [firstpage_image] =>[orig_patent_app_number] => 11807272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/807272
Memory architecture having local column select lines May 23, 2007 Issued
Array ( [id] => 4976039 [patent_doc_number] => 20070217270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Synchronous semiconductor memory device having on-die termination circuit and on-die termination method' [patent_app_type] => utility [patent_app_number] => 11/802443 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4858 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20070217270.pdf [firstpage_image] =>[orig_patent_app_number] => 11802443 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/802443
Synchronous semiconductor memory device having on-die termination circuit and on-die termination method May 22, 2007 Issued
Array ( [id] => 5061649 [patent_doc_number] => 20070223288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Circuit and method for adjusting threshold drift over temperature in a CMOS receiver' [patent_app_type] => utility [patent_app_number] => 11/804092 [patent_app_country] => US [patent_app_date] => 2007-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3671 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20070223288.pdf [firstpage_image] =>[orig_patent_app_number] => 11804092 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/804092
Circuit and method for adjusting threshold drift over temperature in a CMOS receiver May 16, 2007 Abandoned
Array ( [id] => 603493 [patent_doc_number] => 07433263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Multi-port semiconductor device and method thereof' [patent_app_type] => utility [patent_app_number] => 11/798709 [patent_app_country] => US [patent_app_date] => 2007-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 12605 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/433/07433263.pdf [firstpage_image] =>[orig_patent_app_number] => 11798709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/798709
Multi-port semiconductor device and method thereof May 15, 2007 Issued
Array ( [id] => 4777344 [patent_doc_number] => 20080285342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Method of Programming a Nonvolatile Memory Cell and Related Memory Array' [patent_app_type] => utility [patent_app_number] => 11/748459 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5611 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20080285342.pdf [firstpage_image] =>[orig_patent_app_number] => 11748459 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/748459
Method of programming a nonvolatile memory cell and related memory array May 13, 2007 Issued
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