Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7600837 [patent_doc_number] => 07385872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Method and apparatus for increasing clock frequency and data rate for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/581350 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6629 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/385/07385872.pdf [firstpage_image] =>[orig_patent_app_number] => 11581350 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/581350
Method and apparatus for increasing clock frequency and data rate for semiconductor devices Oct 16, 2006 Issued
Array ( [id] => 592097 [patent_doc_number] => 07450436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Device recoverable purge for flash storage device' [patent_app_type] => utility [patent_app_number] => 11/582783 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6925 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/450/07450436.pdf [firstpage_image] =>[orig_patent_app_number] => 11582783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/582783
Device recoverable purge for flash storage device Oct 16, 2006 Issued
Array ( [id] => 5036509 [patent_doc_number] => 20070101048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Verified purge for flash storage device' [patent_app_type] => utility [patent_app_number] => 11/582728 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6909 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101048.pdf [firstpage_image] =>[orig_patent_app_number] => 11582728 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/582728
Verified purge for flash storage device Oct 16, 2006 Abandoned
Array ( [id] => 5158660 [patent_doc_number] => 20070171704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'High-bandwidth magnetoresistive random access memory devices and methods of operation thereof' [patent_app_type] => utility [patent_app_number] => 11/581466 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14020 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20070171704.pdf [firstpage_image] =>[orig_patent_app_number] => 11581466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/581466
High-bandwidth magnetoresistive random access memory devices and methods of operation thereof Oct 16, 2006 Issued
Array ( [id] => 293399 [patent_doc_number] => 07545697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Semiconductor device in which a memory array is refreshed based on an address signal' [patent_app_type] => utility [patent_app_number] => 11/580895 [patent_app_country] => US [patent_app_date] => 2006-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 6734 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/545/07545697.pdf [firstpage_image] =>[orig_patent_app_number] => 11580895 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/580895
Semiconductor device in which a memory array is refreshed based on an address signal Oct 15, 2006 Issued
Array ( [id] => 5032419 [patent_doc_number] => 20070096958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Voltage control circuit and semiconductor device having the voltage control circuit' [patent_app_type] => utility [patent_app_number] => 11/580191 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9427 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096958.pdf [firstpage_image] =>[orig_patent_app_number] => 11580191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/580191
Voltage control circuit and semiconductor device having the voltage control circuit Oct 12, 2006 Issued
Array ( [id] => 4544573 [patent_doc_number] => 07889584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Semiconductor memory device having input first-stage circuit' [patent_app_type] => utility [patent_app_number] => 11/580275 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5511 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889584.pdf [firstpage_image] =>[orig_patent_app_number] => 11580275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/580275
Semiconductor memory device having input first-stage circuit Oct 12, 2006 Issued
Array ( [id] => 5214884 [patent_doc_number] => 20070103964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Resistive memory devices including selected reference memory cells and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 11/580766 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6759 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103964.pdf [firstpage_image] =>[orig_patent_app_number] => 11580766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/580766
Resistive memory devices including selected reference memory cells and methods of operating the same Oct 12, 2006 Abandoned
Array ( [id] => 5537934 [patent_doc_number] => 20090219739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'Range-Matching Cell and Content Addressable Memories Using the Same' [patent_app_type] => utility [patent_app_number] => 12/223552 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20090219739.pdf [firstpage_image] =>[orig_patent_app_number] => 12223552 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/223552
Range-Matching Cell and Content Addressable Memories Using the Same Sep 14, 2006 Abandoned
Array ( [id] => 838468 [patent_doc_number] => 07394695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells' [patent_app_type] => utility [patent_app_number] => 11/511488 [patent_app_country] => US [patent_app_date] => 2006-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 81 [patent_no_of_words] => 61537 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394695.pdf [firstpage_image] =>[orig_patent_app_number] => 11511488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/511488
Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells Aug 28, 2006 Issued
Array ( [id] => 926340 [patent_doc_number] => 07317640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'Nonvolatile memory with erasable parts' [patent_app_type] => utility [patent_app_number] => 11/504017 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8131 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/317/07317640.pdf [firstpage_image] =>[orig_patent_app_number] => 11504017 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504017
Nonvolatile memory with erasable parts Aug 14, 2006 Issued
Array ( [id] => 5607122 [patent_doc_number] => 20060268638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Open digit line array architecture for a memory array' [patent_app_type] => utility [patent_app_number] => 11/500786 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6884 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20060268638.pdf [firstpage_image] =>[orig_patent_app_number] => 11500786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500786
Open digit line array architecture for a memory array Aug 6, 2006 Issued
Array ( [id] => 419632 [patent_doc_number] => 07277310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Open digit line array architecture for a memory array' [patent_app_type] => utility [patent_app_number] => 11/501144 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6909 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/277/07277310.pdf [firstpage_image] =>[orig_patent_app_number] => 11501144 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/501144
Open digit line array architecture for a memory array Aug 6, 2006 Issued
Array ( [id] => 895163 [patent_doc_number] => 07345937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Open digit line array architecture for a memory array' [patent_app_type] => utility [patent_app_number] => 11/501143 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6909 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/345/07345937.pdf [firstpage_image] =>[orig_patent_app_number] => 11501143 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/501143
Open digit line array architecture for a memory array Aug 6, 2006 Issued
Array ( [id] => 6588960 [patent_doc_number] => 20100097836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Memory Bitcell and Method of Using the Same' [patent_app_type] => utility [patent_app_number] => 11/989878 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1826 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097836.pdf [firstpage_image] =>[orig_patent_app_number] => 11989878 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/989878
Memory Bitcell and Method of Using the Same Aug 2, 2006 Abandoned
Array ( [id] => 6564859 [patent_doc_number] => 20100128547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD OF MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/996694 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6850 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128547.pdf [firstpage_image] =>[orig_patent_app_number] => 11996694 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/996694
SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD OF MEMORY SYSTEM Jul 18, 2006 Abandoned
Array ( [id] => 5660271 [patent_doc_number] => 20060250867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Adaptive algorithim for MRAM manufacturing' [patent_app_type] => utility [patent_app_number] => 11/486192 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3862 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250867.pdf [firstpage_image] =>[orig_patent_app_number] => 11486192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486192
Adaptive algorithm for MRAM manufacturing Jul 12, 2006 Issued
Array ( [id] => 5660270 [patent_doc_number] => 20060250866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Adaptive algorithm for MRAM manufacturing' [patent_app_type] => utility [patent_app_number] => 11/485196 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3858 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250866.pdf [firstpage_image] =>[orig_patent_app_number] => 11485196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485196
Adaptive algorithm for MRAM manufacturing Jul 11, 2006 Issued
Array ( [id] => 921087 [patent_doc_number] => 07321519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Adaptive algorithm for MRAM manufacturing' [patent_app_type] => utility [patent_app_number] => 11/485195 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3870 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321519.pdf [firstpage_image] =>[orig_patent_app_number] => 11485195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485195
Adaptive algorithm for MRAM manufacturing Jul 11, 2006 Issued
Array ( [id] => 5660280 [patent_doc_number] => 20060250876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/483649 [patent_app_country] => US [patent_app_date] => 2006-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9880 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20060250876.pdf [firstpage_image] =>[orig_patent_app_number] => 11483649 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/483649
Semiconductor device with power down arrangement for reduce power consumption Jul 10, 2006 Issued
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