Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 327701 [patent_doc_number] => 07515482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Pipe latch device of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/477384 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6088 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/515/07515482.pdf [firstpage_image] =>[orig_patent_app_number] => 11477384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/477384
Pipe latch device of semiconductor memory device Jun 29, 2006 Issued
Array ( [id] => 592140 [patent_doc_number] => 07450440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Circuit for initializing a pipe latch unit in a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/478123 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4066 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/450/07450440.pdf [firstpage_image] =>[orig_patent_app_number] => 11478123 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/478123
Circuit for initializing a pipe latch unit in a semiconductor memory device Jun 29, 2006 Issued
Array ( [id] => 5919492 [patent_doc_number] => 20060239061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Memory system and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/451307 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7487 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20060239061.pdf [firstpage_image] =>[orig_patent_app_number] => 11451307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451307
Memory system and semiconductor integrated circuit Jun 12, 2006 Issued
Array ( [id] => 374263 [patent_doc_number] => 07474569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Two-element magnetic memory cell' [patent_app_type] => utility [patent_app_number] => 11/440966 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6691 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/474/07474569.pdf [firstpage_image] =>[orig_patent_app_number] => 11440966 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/440966
Two-element magnetic memory cell May 24, 2006 Issued
Array ( [id] => 5153135 [patent_doc_number] => 20070036017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Semiconductor memory device and a refresh clock signal generator thereof' [patent_app_type] => utility [patent_app_number] => 11/438926 [patent_app_country] => US [patent_app_date] => 2006-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5582 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20070036017.pdf [firstpage_image] =>[orig_patent_app_number] => 11438926 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/438926
Semiconductor memory device and a refresh clock signal generator thereof May 22, 2006 Issued
Array ( [id] => 271474 [patent_doc_number] => 07564713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Semiconductor integrated circuit device wherein during data write a potential transferred to each bit line is changed in accordance with program order of program data' [patent_app_type] => utility [patent_app_number] => 11/411940 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 38 [patent_no_of_words] => 9473 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564713.pdf [firstpage_image] =>[orig_patent_app_number] => 11411940 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/411940
Semiconductor integrated circuit device wherein during data write a potential transferred to each bit line is changed in accordance with program order of program data Apr 26, 2006 Issued
Array ( [id] => 5833459 [patent_doc_number] => 20060245289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/412122 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4850 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245289.pdf [firstpage_image] =>[orig_patent_app_number] => 11412122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/412122
Semiconductor integrated circuit with power-reducing standby state Apr 26, 2006 Issued
Array ( [id] => 5223987 [patent_doc_number] => 20070253253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Multiple select gates with non-volatile memory cells' [patent_app_type] => utility [patent_app_number] => 11/411376 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10386 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20070253253.pdf [firstpage_image] =>[orig_patent_app_number] => 11411376 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/411376
Multiple select gates with non-volatile memory cells Apr 25, 2006 Issued
Array ( [id] => 581566 [patent_doc_number] => 07463518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Layout structure for use in flash memory device' [patent_app_type] => utility [patent_app_number] => 11/409950 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2193 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463518.pdf [firstpage_image] =>[orig_patent_app_number] => 11409950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409950
Layout structure for use in flash memory device Apr 24, 2006 Issued
Array ( [id] => 588241 [patent_doc_number] => 07457143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Memory device with shared reference and method' [patent_app_type] => utility [patent_app_number] => 11/410432 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1751 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/457/07457143.pdf [firstpage_image] =>[orig_patent_app_number] => 11410432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/410432
Memory device with shared reference and method Apr 24, 2006 Issued
Array ( [id] => 824501 [patent_doc_number] => 07405976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Nonvolatile semiconductor memory and method for controlling the same' [patent_app_type] => utility [patent_app_number] => 11/410136 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 13581 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405976.pdf [firstpage_image] =>[orig_patent_app_number] => 11410136 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/410136
Nonvolatile semiconductor memory and method for controlling the same Apr 24, 2006 Issued
Array ( [id] => 5147285 [patent_doc_number] => 20070047339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Memory control device and memory control method thereof' [patent_app_type] => utility [patent_app_number] => 11/410018 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3980 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20070047339.pdf [firstpage_image] =>[orig_patent_app_number] => 11410018 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/410018
Method for error compensation and a memory control device adapted for error compensation Apr 24, 2006 Issued
Array ( [id] => 834782 [patent_doc_number] => 07397691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Static random access memory cell with improved stability' [patent_app_type] => utility [patent_app_number] => 11/409858 [patent_app_country] => US [patent_app_date] => 2006-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4440 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397691.pdf [firstpage_image] =>[orig_patent_app_number] => 11409858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409858
Static random access memory cell with improved stability Apr 23, 2006 Issued
Array ( [id] => 594300 [patent_doc_number] => 07443708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Low resistance plate line bus architecture' [patent_app_type] => utility [patent_app_number] => 11/409628 [patent_app_country] => US [patent_app_date] => 2006-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9149 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443708.pdf [firstpage_image] =>[orig_patent_app_number] => 11409628 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409628
Low resistance plate line bus architecture Apr 23, 2006 Issued
Array ( [id] => 804690 [patent_doc_number] => 07423903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Single-gate non-volatile memory and operation method thereof' [patent_app_type] => utility [patent_app_number] => 11/403858 [patent_app_country] => US [patent_app_date] => 2006-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3641 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/423/07423903.pdf [firstpage_image] =>[orig_patent_app_number] => 11403858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/403858
Single-gate non-volatile memory and operation method thereof Apr 13, 2006 Issued
Array ( [id] => 486937 [patent_doc_number] => 07221593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Non-volatile memory device with erase address register' [patent_app_type] => utility [patent_app_number] => 11/402549 [patent_app_country] => US [patent_app_date] => 2006-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4307 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221593.pdf [firstpage_image] =>[orig_patent_app_number] => 11402549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/402549
Non-volatile memory device with erase address register Apr 11, 2006 Issued
Array ( [id] => 821953 [patent_doc_number] => 07408832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Memory control method and apparatuses' [patent_app_type] => utility [patent_app_number] => 11/385190 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2156 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/408/07408832.pdf [firstpage_image] =>[orig_patent_app_number] => 11385190 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385190
Memory control method and apparatuses Mar 20, 2006 Issued
Array ( [id] => 5061637 [patent_doc_number] => 20070223276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Non-volatile memory wih controlled program/erase' [patent_app_type] => utility [patent_app_number] => 11/385108 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20070223276.pdf [firstpage_image] =>[orig_patent_app_number] => 11385108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385108
Non-volatile memory with controlled program/erase Mar 20, 2006 Issued
Array ( [id] => 5073040 [patent_doc_number] => 20070013015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Magnetoresistive effect element and magnetic memory' [patent_app_type] => utility [patent_app_number] => 11/378358 [patent_app_country] => US [patent_app_date] => 2006-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6776 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20070013015.pdf [firstpage_image] =>[orig_patent_app_number] => 11378358 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378358
Magnetoresistive effect element and magnetic memory Mar 19, 2006 Issued
Array ( [id] => 5752605 [patent_doc_number] => 20060221754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/378384 [patent_app_country] => US [patent_app_date] => 2006-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 16273 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20060221754.pdf [firstpage_image] =>[orig_patent_app_number] => 11378384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378384
Semiconductor memory device having a hierarchical bit line structure Mar 19, 2006 Issued
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