Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 387532 [patent_doc_number] => 07304903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Sense amplifier circuit' [patent_app_type] => utility [patent_app_number] => 11/337348 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3837 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304903.pdf [firstpage_image] =>[orig_patent_app_number] => 11337348 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/337348
Sense amplifier circuit Jan 22, 2006 Issued
Array ( [id] => 879319 [patent_doc_number] => 07359280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Layout structure for sub word line drivers and method thereof' [patent_app_type] => utility [patent_app_number] => 11/336831 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8778 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/359/07359280.pdf [firstpage_image] =>[orig_patent_app_number] => 11336831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336831
Layout structure for sub word line drivers and method thereof Jan 22, 2006 Issued
Array ( [id] => 517730 [patent_doc_number] => 07196932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells' [patent_app_type] => utility [patent_app_number] => 11/336944 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 81 [patent_no_of_words] => 61567 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196932.pdf [firstpage_image] =>[orig_patent_app_number] => 11336944 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336944
Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells Jan 22, 2006 Issued
Array ( [id] => 897828 [patent_doc_number] => 07342834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Data storage having injected hot carriers and erasable when selectively exposed to ambient light radiation' [patent_app_type] => utility [patent_app_number] => 11/335610 [patent_app_country] => US [patent_app_date] => 2006-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5136 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/342/07342834.pdf [firstpage_image] =>[orig_patent_app_number] => 11335610 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/335610
Data storage having injected hot carriers and erasable when selectively exposed to ambient light radiation Jan 19, 2006 Issued
Array ( [id] => 866859 [patent_doc_number] => 07369440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Method, circuit and systems for erasing one or more non-volatile memory cells' [patent_app_type] => utility [patent_app_number] => 11/335318 [patent_app_country] => US [patent_app_date] => 2006-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5063 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/369/07369440.pdf [firstpage_image] =>[orig_patent_app_number] => 11335318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/335318
Method, circuit and systems for erasing one or more non-volatile memory cells Jan 18, 2006 Issued
Array ( [id] => 5187143 [patent_doc_number] => 20070165451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Enhanced MRAM reference bit programming structure' [patent_app_type] => utility [patent_app_number] => 11/335344 [patent_app_country] => US [patent_app_date] => 2006-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165451.pdf [firstpage_image] =>[orig_patent_app_number] => 11335344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/335344
Enhanced MRAM reference bit programming structure Jan 18, 2006 Issued
Array ( [id] => 5595032 [patent_doc_number] => 20060158948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 11/333344 [patent_app_country] => US [patent_app_date] => 2006-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5722 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20060158948.pdf [firstpage_image] =>[orig_patent_app_number] => 11333344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333344
Memory device Jan 17, 2006 Abandoned
Array ( [id] => 5595036 [patent_doc_number] => 20060158952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'SRAM device capable of performing burst operation' [patent_app_type] => utility [patent_app_number] => 11/333650 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8940 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20060158952.pdf [firstpage_image] =>[orig_patent_app_number] => 11333650 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333650
SRAM device capable of performing burst operation Jan 16, 2006 Issued
Array ( [id] => 459629 [patent_doc_number] => 07245532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Nonvolatile semiconductor memory device which stores multi-value information' [patent_app_type] => utility [patent_app_number] => 11/332206 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 17699 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245532.pdf [firstpage_image] =>[orig_patent_app_number] => 11332206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/332206
Nonvolatile semiconductor memory device which stores multi-value information Jan 16, 2006 Issued
Array ( [id] => 5692820 [patent_doc_number] => 20060152966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage' [patent_app_type] => utility [patent_app_number] => 11/332122 [patent_app_country] => US [patent_app_date] => 2006-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6944 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20060152966.pdf [firstpage_image] =>[orig_patent_app_number] => 11332122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/332122
Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage Jan 12, 2006 Issued
Array ( [id] => 5218577 [patent_doc_number] => 20070159888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'FLASH MEMORY DEVICES WITH TRIMMED ANALOG VOLTAGES' [patent_app_type] => utility [patent_app_number] => 11/332567 [patent_app_country] => US [patent_app_date] => 2006-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11931 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20070159888.pdf [firstpage_image] =>[orig_patent_app_number] => 11332567 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/332567
Flash memory devices with trimmed analog voltages Jan 11, 2006 Issued
Array ( [id] => 5731498 [patent_doc_number] => 20060256612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Phase change memory device and method of driving word line thereof' [patent_app_type] => utility [patent_app_number] => 11/303910 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20060256612.pdf [firstpage_image] =>[orig_patent_app_number] => 11303910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/303910
Phase change memory device and method of driving word line thereof Dec 18, 2005 Issued
Array ( [id] => 399223 [patent_doc_number] => 07295466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Use of recovery transistors during write operations to prevent disturbance of unselected cells' [patent_app_type] => utility [patent_app_number] => 11/303368 [patent_app_country] => US [patent_app_date] => 2005-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2549 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295466.pdf [firstpage_image] =>[orig_patent_app_number] => 11303368 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/303368
Use of recovery transistors during write operations to prevent disturbance of unselected cells Dec 15, 2005 Issued
Array ( [id] => 926344 [patent_doc_number] => 07317644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-08 [patent_title] => 'Signal timing for I/O' [patent_app_type] => utility [patent_app_number] => 11/303250 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3996 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/317/07317644.pdf [firstpage_image] =>[orig_patent_app_number] => 11303250 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/303250
Signal timing for I/O Dec 14, 2005 Issued
Array ( [id] => 5647405 [patent_doc_number] => 20060133137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Voltage-controlled magnetization reversal writing type magnetic random access memory device and method of writing and reading information using the same' [patent_app_type] => utility [patent_app_number] => 11/303584 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5659 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20060133137.pdf [firstpage_image] =>[orig_patent_app_number] => 11303584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/303584
Voltage-controlled magnetization reversal writing type magnetic random access memory device and method of writing and reading information using the same Dec 14, 2005 Issued
Array ( [id] => 5118309 [patent_doc_number] => 20070140023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Integrated dynamic random access memory chip' [patent_app_type] => utility [patent_app_number] => 11/304060 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20070140023.pdf [firstpage_image] =>[orig_patent_app_number] => 11304060 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304060
Integrated dynamic random access memory chip Dec 14, 2005 Abandoned
Array ( [id] => 5251861 [patent_doc_number] => 20070133317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Multiple power supplies for the driving circuit of local word line driver of DRAM' [patent_app_type] => utility [patent_app_number] => 11/304416 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3375 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133317.pdf [firstpage_image] =>[orig_patent_app_number] => 11304416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304416
Multiple power supplies for the driving circuit of local word line driver of DRAM Dec 13, 2005 Issued
Array ( [id] => 478676 [patent_doc_number] => 07227807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Method of configuring memory cell array block, method of addressing the same, semiconductor memory device and memory cell array block' [patent_app_type] => utility [patent_app_number] => 11/302606 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6447 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227807.pdf [firstpage_image] =>[orig_patent_app_number] => 11302606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302606
Method of configuring memory cell array block, method of addressing the same, semiconductor memory device and memory cell array block Dec 13, 2005 Issued
Array ( [id] => 416665 [patent_doc_number] => 07280405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Integrator-based current sensing circuit for reading memory cells' [patent_app_type] => utility [patent_app_number] => 11/304168 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 5382 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/280/07280405.pdf [firstpage_image] =>[orig_patent_app_number] => 11304168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304168
Integrator-based current sensing circuit for reading memory cells Dec 12, 2005 Issued
Array ( [id] => 5911310 [patent_doc_number] => 20060126372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Circuits for driving FRAM' [patent_app_type] => utility [patent_app_number] => 11/301920 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5511 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20060126372.pdf [firstpage_image] =>[orig_patent_app_number] => 11301920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301920
Circuits for driving FRAM Dec 12, 2005 Issued
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