Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8258790 [patent_doc_number] => 08208293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Programmable phase-change memory and method therefor' [patent_app_type] => utility [patent_app_number] => 11/721432 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3291 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11721432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/721432
Programmable phase-change memory and method therefor Dec 8, 2005 Issued
Array ( [id] => 5214900 [patent_doc_number] => 20070103980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Method for operating a semiconductor memory device and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/272044 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7243 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103980.pdf [firstpage_image] =>[orig_patent_app_number] => 11272044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/272044
Method for operating a semiconductor memory device and semiconductor memory device Nov 9, 2005 Abandoned
Array ( [id] => 455633 [patent_doc_number] => 07248530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Integrated semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/261912 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7741 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248530.pdf [firstpage_image] =>[orig_patent_app_number] => 11261912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261912
Integrated semiconductor memory device Oct 30, 2005 Issued
Array ( [id] => 409908 [patent_doc_number] => 07286407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Semiconductor device and method for controlling the same' [patent_app_type] => utility [patent_app_number] => 11/261743 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5913 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286407.pdf [firstpage_image] =>[orig_patent_app_number] => 11261743 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261743
Semiconductor device and method for controlling the same Oct 27, 2005 Issued
Array ( [id] => 921084 [patent_doc_number] => 07321517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/260200 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8363 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321517.pdf [firstpage_image] =>[orig_patent_app_number] => 11260200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260200
Semiconductor memory device Oct 27, 2005 Issued
Array ( [id] => 531802 [patent_doc_number] => 07187609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Self refresh circuit of PSRAM for real access time measurement and operating method for the same' [patent_app_type] => utility [patent_app_number] => 11/261152 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6800 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187609.pdf [firstpage_image] =>[orig_patent_app_number] => 11261152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261152
Self refresh circuit of PSRAM for real access time measurement and operating method for the same Oct 27, 2005 Issued
Array ( [id] => 463432 [patent_doc_number] => 07242600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground' [patent_app_type] => utility [patent_app_number] => 11/262062 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4356 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242600.pdf [firstpage_image] =>[orig_patent_app_number] => 11262062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/262062
Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground Oct 27, 2005 Issued
Array ( [id] => 451343 [patent_doc_number] => 07251169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Voltage supply circuit and semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/260196 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13386 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/251/07251169.pdf [firstpage_image] =>[orig_patent_app_number] => 11260196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260196
Voltage supply circuit and semiconductor memory Oct 27, 2005 Issued
Array ( [id] => 5600962 [patent_doc_number] => 20060291307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Semiconductor memory and burn-in test method of semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/260486 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11468 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20060291307.pdf [firstpage_image] =>[orig_patent_app_number] => 11260486 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260486
Semiconductor memory and burn-in test method of semiconductor memory Oct 27, 2005 Issued
Array ( [id] => 409894 [patent_doc_number] => 07286395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells' [patent_app_type] => utility [patent_app_number] => 11/260778 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6956 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286395.pdf [firstpage_image] =>[orig_patent_app_number] => 11260778 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260778
Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells Oct 26, 2005 Issued
Array ( [id] => 581447 [patent_doc_number] => 07463509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Magneto-resistive RAM having multi-bit cell array structure' [patent_app_type] => utility [patent_app_number] => 11/260602 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6731 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463509.pdf [firstpage_image] =>[orig_patent_app_number] => 11260602 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260602
Magneto-resistive RAM having multi-bit cell array structure Oct 26, 2005 Issued
Array ( [id] => 5033210 [patent_doc_number] => 20070097749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method for programming of multi-state non-volatile memory using smart verify' [patent_app_type] => utility [patent_app_number] => 11/260658 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13241 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20070097749.pdf [firstpage_image] =>[orig_patent_app_number] => 11260658 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260658
Method for programming of multi-state non-volatile memory using smart verify Oct 26, 2005 Issued
Array ( [id] => 5654255 [patent_doc_number] => 20060139990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Pre-written volatile memory cell' [patent_app_type] => utility [patent_app_number] => 11/261396 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4789 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139990.pdf [firstpage_image] =>[orig_patent_app_number] => 11261396 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261396
Pre-written volatile memory cell Oct 24, 2005 Issued
Array ( [id] => 475546 [patent_doc_number] => 07230856 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'High-speed multiplexer latch' [patent_app_type] => utility [patent_app_number] => 11/259342 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2748 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230856.pdf [firstpage_image] =>[orig_patent_app_number] => 11259342 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/259342
High-speed multiplexer latch Oct 23, 2005 Issued
Array ( [id] => 5879811 [patent_doc_number] => 20060028893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Semiconductor memory device, refresh control method thereof, and test method thereof' [patent_app_type] => utility [patent_app_number] => 11/249454 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17788 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20060028893.pdf [firstpage_image] =>[orig_patent_app_number] => 11249454 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/249454
Semiconductor memory device, refresh control method thereof, and test method thereof Oct 13, 2005 Issued
Array ( [id] => 5612787 [patent_doc_number] => 20060114715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Memory' [patent_app_type] => utility [patent_app_number] => 11/248812 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8072 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20060114715.pdf [firstpage_image] =>[orig_patent_app_number] => 11248812 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/248812
Memory including a transfer gate and a storage element Oct 10, 2005 Issued
Array ( [id] => 377911 [patent_doc_number] => 07313015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Storage element and memory including a storage layer a magnetization fixed layer and a drive layer' [patent_app_type] => utility [patent_app_number] => 11/241315 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9893 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313015.pdf [firstpage_image] =>[orig_patent_app_number] => 11241315 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241315
Storage element and memory including a storage layer a magnetization fixed layer and a drive layer Sep 29, 2005 Issued
Array ( [id] => 517618 [patent_doc_number] => 07196923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'Bitcell layout' [patent_app_type] => utility [patent_app_number] => 11/241390 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2958 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196923.pdf [firstpage_image] =>[orig_patent_app_number] => 11241390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241390
Bitcell layout Sep 29, 2005 Issued
Array ( [id] => 409867 [patent_doc_number] => 07286379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Content addressable memory (CAM) architecture and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/221636 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 9896 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286379.pdf [firstpage_image] =>[orig_patent_app_number] => 11221636 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221636
Content addressable memory (CAM) architecture and method of operating the same Sep 7, 2005 Issued
Array ( [id] => 879309 [patent_doc_number] => 07359275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Reduced size dual-port SRAM cell' [patent_app_type] => utility [patent_app_number] => 11/222390 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9491 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/359/07359275.pdf [firstpage_image] =>[orig_patent_app_number] => 11222390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/222390
Reduced size dual-port SRAM cell Sep 7, 2005 Issued
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