
Hoai V. Ho
Examiner (ID: 15701)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2312, 2511 |
| Total Applications | 2584 |
| Issued Applications | 2371 |
| Pending Applications | 99 |
| Abandoned Applications | 149 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 682544
[patent_doc_number] => 07085192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 11/004796
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5192
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/085/07085192.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004796
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004796 | Semiconductor integrated circuit device | Dec 6, 2004 | Issued |
Array
(
[id] => 5775509
[patent_doc_number] => 20060104149
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-18
[patent_title] => 'Synchronous semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/004842
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1965
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20060104149.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004842
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004842 | Synchronous semiconductor memory device | Dec 6, 2004 | Issued |
Array
(
[id] => 7096338
[patent_doc_number] => 20050128796
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Method for improving the read signal in a memory having passive memory elements'
[patent_app_type] => utility
[patent_app_number] => 11/004880
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4384
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20050128796.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004880
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004880 | Method for improving the read signal in a memory having passive memory elements | Dec 6, 2004 | Issued |
Array
(
[id] => 7606491
[patent_doc_number] => 07099228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-29
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/004806
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3802
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/099/07099228.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004806
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004806 | Semiconductor memory device | Dec 6, 2004 | Issued |
Array
(
[id] => 684200
[patent_doc_number] => 07082061
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-25
[patent_title] => 'Memory array with low power bit line precharge'
[patent_app_type] => utility
[patent_app_number] => 11/003092
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6353
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/082/07082061.pdf
[firstpage_image] =>[orig_patent_app_number] => 11003092
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/003092 | Memory array with low power bit line precharge | Dec 2, 2004 | Issued |
Array
(
[id] => 657264
[patent_doc_number] => 07110295
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Semiconductor data processing device'
[patent_app_type] => utility
[patent_app_number] => 11/002802
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 36
[patent_no_of_words] => 17332
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/110/07110295.pdf
[firstpage_image] =>[orig_patent_app_number] => 11002802
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/002802 | Semiconductor data processing device | Dec 2, 2004 | Issued |
Array
(
[id] => 538353
[patent_doc_number] => 07184359
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-02-27
[patent_title] => 'System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock'
[patent_app_type] => utility
[patent_app_number] => 11/003292
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 6527
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/184/07184359.pdf
[firstpage_image] =>[orig_patent_app_number] => 11003292
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/003292 | System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock | Dec 2, 2004 | Issued |
Array
(
[id] => 5840548
[patent_doc_number] => 20060120175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'MEMORY ARRAY WITH FAST BIT LINE PRECHARGE'
[patent_app_type] => utility
[patent_app_number] => 11/004148
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6697
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20060120175.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004148
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004148 | Memory array with fast bit line precharge | Dec 2, 2004 | Issued |
Array
(
[id] => 538024
[patent_doc_number] => 07184333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'Semiconductor memory having a dummy signal line connected to dummy memory cell'
[patent_app_type] => utility
[patent_app_number] => 11/002894
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7982
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/184/07184333.pdf
[firstpage_image] =>[orig_patent_app_number] => 11002894
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/002894 | Semiconductor memory having a dummy signal line connected to dummy memory cell | Dec 2, 2004 | Issued |
Array
(
[id] => 537924
[patent_doc_number] => 07184324
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'Semiconductor memory device having a single input terminal to select a buffer and method of testing the same'
[patent_app_type] => utility
[patent_app_number] => 11/004684
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4983
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/184/07184324.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004684
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004684 | Semiconductor memory device having a single input terminal to select a buffer and method of testing the same | Dec 2, 2004 | Issued |
Array
(
[id] => 5840465
[patent_doc_number] => 20060120127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'SYSTEMS AND METHODS FOR PREVENTING MALFUNCTION OF CONTENT ADDRESSABLE MEMORY RESULTING FROM CONCURRENT WRITE AND LOOKUP OPERATIONS'
[patent_app_type] => utility
[patent_app_number] => 11/003084
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7906
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0120/20060120127.pdf
[firstpage_image] =>[orig_patent_app_number] => 11003084
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/003084 | Systems and methods for preventing malfunction of content addressable memory resulting from concurrent write and lookup operations | Dec 2, 2004 | Issued |
Array
(
[id] => 682515
[patent_doc_number] => 07085175
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Word line driver circuit for a static random access memory and method therefor'
[patent_app_type] => utility
[patent_app_number] => 10/991910
[patent_app_country] => US
[patent_app_date] => 2004-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2581
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/085/07085175.pdf
[firstpage_image] =>[orig_patent_app_number] => 10991910
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/991910 | Word line driver circuit for a static random access memory and method therefor | Nov 17, 2004 | Issued |
Array
(
[id] => 796222
[patent_doc_number] => 07430141
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-30
[patent_title] => 'Method and apparatus for memory data deskewing'
[patent_app_type] => utility
[patent_app_number] => 10/991010
[patent_app_country] => US
[patent_app_date] => 2004-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2758
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/430/07430141.pdf
[firstpage_image] =>[orig_patent_app_number] => 10991010
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/991010 | Method and apparatus for memory data deskewing | Nov 15, 2004 | Issued |
Array
(
[id] => 7247452
[patent_doc_number] => 20050073900
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Reduced signal swing in bit lines in a CAM'
[patent_app_type] => utility
[patent_app_number] => 10/982892
[patent_app_country] => US
[patent_app_date] => 2004-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5562
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20050073900.pdf
[firstpage_image] =>[orig_patent_app_number] => 10982892
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/982892 | Reduced signal swing in bit lines in a CAM | Nov 7, 2004 | Issued |
Array
(
[id] => 665561
[patent_doc_number] => 07102918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-05
[patent_title] => 'MRAM having two write conductors'
[patent_app_type] => utility
[patent_app_number] => 10/983776
[patent_app_country] => US
[patent_app_date] => 2004-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 3501
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/102/07102918.pdf
[firstpage_image] =>[orig_patent_app_number] => 10983776
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/983776 | MRAM having two write conductors | Nov 6, 2004 | Issued |
Array
(
[id] => 5864375
[patent_doc_number] => 20060098505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-11
[patent_title] => 'FAILURE TEST METHOD FOR SPLIT GATE FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 10/904342
[patent_app_country] => US
[patent_app_date] => 2004-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5361
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20060098505.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904342
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904342 | Failure test method for split gate flash memory | Nov 3, 2004 | Issued |
Array
(
[id] => 7621652
[patent_doc_number] => 06977849
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-20
[patent_title] => 'Semiconductor device suitable for system in package'
[patent_app_type] => utility
[patent_app_number] => 10/961146
[patent_app_country] => US
[patent_app_date] => 2004-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 67
[patent_no_of_words] => 32437
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/977/06977849.pdf
[firstpage_image] =>[orig_patent_app_number] => 10961146
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/961146 | Semiconductor device suitable for system in package | Oct 11, 2004 | Issued |
Array
(
[id] => 745582
[patent_doc_number] => 07031198
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-18
[patent_title] => 'Non-volatile semiconductor memory device and method of actuating the same'
[patent_app_type] => utility
[patent_app_number] => 10/953520
[patent_app_country] => US
[patent_app_date] => 2004-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 20
[patent_no_of_words] => 18587
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 440
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/031/07031198.pdf
[firstpage_image] =>[orig_patent_app_number] => 10953520
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/953520 | Non-volatile semiconductor memory device and method of actuating the same | Sep 29, 2004 | Issued |
Array
(
[id] => 674413
[patent_doc_number] => 07092279
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-08-15
[patent_title] => 'Shared bit line memory device and method'
[patent_app_type] => utility
[patent_app_number] => 10/954047
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 14579
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/092/07092279.pdf
[firstpage_image] =>[orig_patent_app_number] => 10954047
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/954047 | Shared bit line memory device and method | Sep 28, 2004 | Issued |
Array
(
[id] => 624907
[patent_doc_number] => 07139189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-21
[patent_title] => 'State-retentive mixed register file array'
[patent_app_type] => utility
[patent_app_number] => 10/948675
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1633
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/139/07139189.pdf
[firstpage_image] =>[orig_patent_app_number] => 10948675
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/948675 | State-retentive mixed register file array | Sep 23, 2004 | Issued |