Search

Hoai V. Ho

Examiner (ID: 15701)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2312, 2511
Total Applications
2584
Issued Applications
2371
Pending Applications
99
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 405539 [patent_doc_number] => 07289374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Circuit and method for adjusting threshold drift over temperature in a CMOS receiver' [patent_app_type] => utility [patent_app_number] => 10/882592 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3656 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/289/07289374.pdf [firstpage_image] =>[orig_patent_app_number] => 10882592 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/882592
Circuit and method for adjusting threshold drift over temperature in a CMOS receiver Jun 30, 2004 Issued
Array ( [id] => 768533 [patent_doc_number] => 07009865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Non-volatile ferroelectric cell array circuit using PNPN diode characteristics' [patent_app_type] => utility [patent_app_number] => 10/878312 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5542 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009865.pdf [firstpage_image] =>[orig_patent_app_number] => 10878312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878312
Non-volatile ferroelectric cell array circuit using PNPN diode characteristics Jun 28, 2004 Issued
Array ( [id] => 780926 [patent_doc_number] => 06996027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Synchronous memory device' [patent_app_type] => utility [patent_app_number] => 10/876412 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 8018 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996027.pdf [firstpage_image] =>[orig_patent_app_number] => 10876412 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876412
Synchronous memory device Jun 24, 2004 Issued
Array ( [id] => 788771 [patent_doc_number] => 06987705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Memory device with improved output operation margin' [patent_app_type] => utility [patent_app_number] => 10/875496 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5696 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/987/06987705.pdf [firstpage_image] =>[orig_patent_app_number] => 10875496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875496
Memory device with improved output operation margin Jun 24, 2004 Issued
Array ( [id] => 7414133 [patent_doc_number] => 20040228201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Non-volatile memory erase circuitry' [patent_app_type] => new [patent_app_number] => 10/871919 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20040228201.pdf [firstpage_image] =>[orig_patent_app_number] => 10871919 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/871919
Non-volatile memory erase circuitry Jun 17, 2004 Issued
Array ( [id] => 557380 [patent_doc_number] => 07170817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Access of two synchronous busses with asynchronous clocks to a synchronous single port ram' [patent_app_type] => utility [patent_app_number] => 10/869484 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2405 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170817.pdf [firstpage_image] =>[orig_patent_app_number] => 10869484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/869484
Access of two synchronous busses with asynchronous clocks to a synchronous single port ram Jun 15, 2004 Issued
Array ( [id] => 7274248 [patent_doc_number] => 20040233699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/864173 [patent_app_country] => US [patent_app_date] => 2004-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3732 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233699.pdf [firstpage_image] =>[orig_patent_app_number] => 10864173 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/864173
Method of repairing a failed wordline Jun 7, 2004 Issued
Array ( [id] => 7451750 [patent_doc_number] => 20040196730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Nonvolatile semiconductor memory device which stores multi-value information' [patent_app_type] => new [patent_app_number] => 10/832311 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 17812 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196730.pdf [firstpage_image] =>[orig_patent_app_number] => 10832311 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/832311
Nonvolatile semiconductor memory device which stores multi-value information Apr 26, 2004 Issued
Array ( [id] => 997853 [patent_doc_number] => 06914831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Low voltage current reference' [patent_app_type] => utility [patent_app_number] => 10/822771 [patent_app_country] => US [patent_app_date] => 2004-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3145 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914831.pdf [firstpage_image] =>[orig_patent_app_number] => 10822771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822771
Low voltage current reference Apr 12, 2004 Issued
Array ( [id] => 7429203 [patent_doc_number] => 20040184319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Non-volatile memory erase circuitry' [patent_app_type] => new [patent_app_number] => 10/816386 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20040184319.pdf [firstpage_image] =>[orig_patent_app_number] => 10816386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816386
Non-volatile memory erase circuitry Mar 31, 2004 Issued
Array ( [id] => 5701656 [patent_doc_number] => 20060218341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Two-dimensional data memory' [patent_app_type] => utility [patent_app_number] => 10/548742 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4212 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20060218341.pdf [firstpage_image] =>[orig_patent_app_number] => 10548742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/548742
Two-dimensional data memory Feb 26, 2004 Issued
Array ( [id] => 7421164 [patent_doc_number] => 20040160829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Semiconductor, memory card, and data processing system' [patent_app_type] => new [patent_app_number] => 10/776190 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 19783 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160829.pdf [firstpage_image] =>[orig_patent_app_number] => 10776190 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776190
Semiconductor, memory card, and data processing system Feb 11, 2004 Issued
Array ( [id] => 7225408 [patent_doc_number] => 20040156236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Programmable semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/771320 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7041 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20040156236.pdf [firstpage_image] =>[orig_patent_app_number] => 10771320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/771320
Programmable semiconductor memory Feb 4, 2004 Abandoned
Array ( [id] => 7306366 [patent_doc_number] => 20040141391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Synchronous semiconductor memory device having on-die termination circuit and on-die termination method' [patent_app_type] => new [patent_app_number] => 10/749521 [patent_app_country] => US [patent_app_date] => 2004-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4895 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20040141391.pdf [firstpage_image] =>[orig_patent_app_number] => 10749521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749521
Synchronous semiconductor memory device having on-die termination circuit and on-die termination method Jan 1, 2004 Issued
Array ( [id] => 7320540 [patent_doc_number] => 20040136247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Sending signal through integrated circuit during setup time' [patent_app_type] => new [patent_app_number] => 10/744778 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4850 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20040136247.pdf [firstpage_image] =>[orig_patent_app_number] => 10744778 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744778
Sending signal through integrated circuit during setup time Dec 22, 2003 Issued
Array ( [id] => 7247182 [patent_doc_number] => 20040158773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Test mode control device using nonvolatile ferroelectric memory' [patent_app_type] => new [patent_app_number] => 10/730134 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158773.pdf [firstpage_image] =>[orig_patent_app_number] => 10730134 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/730134
Test mode control device using nonvolatile ferroelectric memory Dec 8, 2003 Issued
Array ( [id] => 1042169 [patent_doc_number] => 06870790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Semiconductor device having a power down mode' [patent_app_type] => utility [patent_app_number] => 10/724781 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9821 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870790.pdf [firstpage_image] =>[orig_patent_app_number] => 10724781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724781
Semiconductor device having a power down mode Dec 1, 2003 Issued
Array ( [id] => 7401761 [patent_doc_number] => 20040105313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Erasing method for p-channel NROM' [patent_app_type] => new [patent_app_number] => 10/712586 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1542 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20040105313.pdf [firstpage_image] =>[orig_patent_app_number] => 10712586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712586
Erasing method for p-channel NROM Nov 11, 2003 Abandoned
Array ( [id] => 1016099 [patent_doc_number] => 06894918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Shared volatile and non-volatile memory' [patent_app_type] => utility [patent_app_number] => 10/697367 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4218 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894918.pdf [firstpage_image] =>[orig_patent_app_number] => 10697367 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697367
Shared volatile and non-volatile memory Oct 29, 2003 Issued
Array ( [id] => 7391598 [patent_doc_number] => 20040083329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system' [patent_app_type] => new [patent_app_number] => 10/686569 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11376 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083329.pdf [firstpage_image] =>[orig_patent_app_number] => 10686569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686569
Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system Oct 16, 2003 Issued
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